llvm-project/llvm/lib/Target/CellSPU
Kalle Raiskila 999da1f3a0 Have SPU handle halfvec stores aligned by 8 bytes.
llvm-svn: 110576
2010-08-09 16:33:00 +00:00
..
AsmPrinter fix some inconsistent line endings, patch by Jakub Staszak! 2010-05-01 17:36:49 +00:00
TargetInfo make -fno-rtti the default unless a directory builds with REQUIRES_RTTI. 2010-01-24 20:43:08 +00:00
CMakeLists.txt Add skeleton target-specific SelectionDAGInfo files. 2010-04-16 23:04:22 +00:00
CellSDKIntrinsics.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
Makefile make -fno-rtti the default unless a directory builds with REQUIRES_RTTI. 2010-01-24 20:43:08 +00:00
README.txt Testing svn access with a note added to documentation. 2010-05-07 18:06:28 +00:00
SPU.h Remove a bunch of integer width predicate functions in favor of MathExtras. 2010-03-29 19:07:58 +00:00
SPU.td - Start moving target-dependent nodes that could be represented by an 2008-12-30 23:28:25 +00:00
SPU64InstrInfo.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
SPU128InstrInfo.td CellSPU: 2009-01-21 04:58:48 +00:00
SPUCallingConv.td Add preliminary v2f32 support for SPU. Like with v2i32, we just 2010-08-02 10:25:47 +00:00
SPUFrameInfo.cpp
SPUFrameInfo.h Remove some unused/redundant code. 2010-07-05 18:40:09 +00:00
SPUHazardRecognizers.cpp eliminate the last DOUTs from the targets. 2009-08-23 06:49:22 +00:00
SPUHazardRecognizers.h Generalize the HazardRecognizer interface so that it can be used 2009-01-15 22:18:12 +00:00
SPUISelDAGToDAG.cpp Make SPU backend handle insertelement and 2010-08-04 13:59:48 +00:00
SPUISelLowering.cpp Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
SPUISelLowering.h Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
SPUInstrBuilder.h Fix constant pool loads, and remove broken versions of addConstantPoolReference. 2008-09-06 01:11:01 +00:00
SPUInstrFormats.td CellSPU: 2009-01-26 22:33:37 +00:00
SPUInstrInfo.cpp Remove the isMoveInstr() hook. 2010-07-16 22:35:46 +00:00
SPUInstrInfo.h Remove the isMoveInstr() hook. 2010-07-16 22:35:46 +00:00
SPUInstrInfo.td Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
SPUMCAsmInfo.cpp Don't pass StringRef by reference. 2010-07-14 22:38:02 +00:00
SPUMCAsmInfo.h Don't pass StringRef by reference. 2010-07-14 22:38:02 +00:00
SPUMachineFunction.h Move per-function state out of TargetLowering subclasses and into 2010-04-17 14:41:14 +00:00
SPUMathInstr.td Add preliminary v2i32 support for SPU backend. As there are no 2010-08-02 08:54:39 +00:00
SPUNodes.td Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
SPUOperands.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
SPURegisterInfo.cpp Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
SPURegisterInfo.h Switch SPU calling convention (function arguments) 2010-07-08 21:15:22 +00:00
SPURegisterInfo.td Add preliminary v2f32 support for SPU. Like with v2i32, we just 2010-08-02 10:25:47 +00:00
SPURegisterNames.h
SPUSchedule.td Make processor FUs unique for given itinerary. This extends the limit of 32 2010-04-18 20:31:01 +00:00
SPUSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSubtarget.cpp Normalize Subtarget constructors to take a target triple string instead of 2009-08-02 22:11:08 +00:00
SPUSubtarget.h indicate what the native integer types for the target are. 2009-11-07 19:07:32 +00:00
SPUTargetMachine.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUTargetMachine.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00

README.txt

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: needed
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===