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llvm-project/llvm/test/MC/Disassembler
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Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
 		2011-07-29 20:26:09 +00:00
..
ARM ARM SRS instruction parsing, diassembly and encoding support. 2011-07-29 20:26:09 +00:00
MBlaze Teach the MBlaze disassembler to disassemble special purpose registers. 2010-12-20 21:18:04 +00:00
X86 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 2011-07-16 02:41:28 +00:00