forked from OSchip/llvm-project
462 lines
15 KiB
LLVM
462 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=ENABLED
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; RUN: llc --disable-x86-lea-opt < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=CHECK -check-prefix=DISABLED
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%struct.anon1 = type { i32, i32, i32 }
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%struct.anon2 = type { i32, [32 x i32], i32 }
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@arr1 = external global [65 x %struct.anon1], align 16
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@arr2 = external global [65 x %struct.anon2], align 16
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define void @test1(i64 %x) nounwind {
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; ENABLED-LABEL: test1:
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; ENABLED: # %bb.0: # %entry
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; ENABLED-NEXT: shlq $2, %rdi
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; ENABLED-NEXT: movl arr1(%rdi,%rdi,2), %ecx
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; ENABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax
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; ENABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %ecx
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; ENABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %ecx
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; ENABLED-NEXT: cmpl $2, %ecx
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; ENABLED-NEXT: je .LBB0_3
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; ENABLED-NEXT: # %bb.1: # %entry
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; ENABLED-NEXT: cmpl $1, %ecx
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; ENABLED-NEXT: jne .LBB0_4
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; ENABLED-NEXT: # %bb.2: # %sw.bb.1
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; ENABLED-NEXT: movl $111, (%rax)
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; ENABLED-NEXT: movl $222, 4(%rax)
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; ENABLED-NEXT: retq
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; ENABLED-NEXT: .LBB0_3: # %sw.bb.2
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; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC
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; ENABLED-NEXT: .LBB0_4: # %sw.epilog
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; ENABLED-NEXT: retq
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;
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; DISABLED-LABEL: test1:
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; DISABLED: # %bb.0: # %entry
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; DISABLED-NEXT: shlq $2, %rdi
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; DISABLED-NEXT: movl arr1(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax
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; DISABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: leaq arr1+8(%rdi,%rdi,2), %rcx
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; DISABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: cmpl $2, %edx
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; DISABLED-NEXT: je .LBB0_3
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; DISABLED-NEXT: # %bb.1: # %entry
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; DISABLED-NEXT: cmpl $1, %edx
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; DISABLED-NEXT: jne .LBB0_4
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; DISABLED-NEXT: # %bb.2: # %sw.bb.1
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; DISABLED-NEXT: movl $111, (%rax)
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; DISABLED-NEXT: movl $222, (%rcx)
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; DISABLED-NEXT: retq
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; DISABLED-NEXT: .LBB0_3: # %sw.bb.2
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; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC
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; DISABLED-NEXT: .LBB0_4: # %sw.epilog
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; DISABLED-NEXT: retq
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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}
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define void @test2(i64 %x) nounwind optsize {
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; ENABLED-LABEL: test2:
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; ENABLED: # %bb.0: # %entry
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; ENABLED-NEXT: shlq $2, %rdi
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; ENABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax
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; ENABLED-NEXT: movl -4(%rax), %ecx
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; ENABLED-NEXT: subl (%rax), %ecx
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; ENABLED-NEXT: addl 4(%rax), %ecx
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; ENABLED-NEXT: cmpl $2, %ecx
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; ENABLED-NEXT: je .LBB1_3
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; ENABLED-NEXT: # %bb.1: # %entry
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; ENABLED-NEXT: cmpl $1, %ecx
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; ENABLED-NEXT: jne .LBB1_4
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; ENABLED-NEXT: # %bb.2: # %sw.bb.1
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; ENABLED-NEXT: movl $111, (%rax)
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; ENABLED-NEXT: movl $222, 4(%rax)
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; ENABLED-NEXT: retq
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; ENABLED-NEXT: .LBB1_3: # %sw.bb.2
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; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC
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; ENABLED-NEXT: .LBB1_4: # %sw.epilog
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; ENABLED-NEXT: retq
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;
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; DISABLED-LABEL: test2:
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; DISABLED: # %bb.0: # %entry
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; DISABLED-NEXT: shlq $2, %rdi
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; DISABLED-NEXT: movl arr1(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: leaq arr1+4(%rdi,%rdi,2), %rax
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; DISABLED-NEXT: subl arr1+4(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: leaq arr1+8(%rdi,%rdi,2), %rcx
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; DISABLED-NEXT: addl arr1+8(%rdi,%rdi,2), %edx
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; DISABLED-NEXT: cmpl $2, %edx
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; DISABLED-NEXT: je .LBB1_3
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; DISABLED-NEXT: # %bb.1: # %entry
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; DISABLED-NEXT: cmpl $1, %edx
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; DISABLED-NEXT: jne .LBB1_4
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; DISABLED-NEXT: # %bb.2: # %sw.bb.1
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; DISABLED-NEXT: movl $111, (%rax)
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; DISABLED-NEXT: movl $222, (%rcx)
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; DISABLED-NEXT: retq
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; DISABLED-NEXT: .LBB1_3: # %sw.bb.2
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; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC
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; DISABLED-NEXT: .LBB1_4: # %sw.epilog
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; DISABLED-NEXT: retq
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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}
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; Check that LEA optimization pass takes into account a resultant address
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; displacement when choosing a LEA instruction for replacing a redundant
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; address recalculation.
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define void @test3(i64 %x) nounwind optsize {
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; ENABLED-LABEL: test3:
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; ENABLED: # %bb.0: # %entry
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; ENABLED-NEXT: movq %rdi, %rax
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; ENABLED-NEXT: shlq $7, %rax
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; ENABLED-NEXT: leaq arr2+132(%rax,%rdi,8), %rcx
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; ENABLED-NEXT: leaq arr2(%rax,%rdi,8), %rax
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; ENABLED-NEXT: movl (%rcx), %edx
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; ENABLED-NEXT: addl (%rax), %edx
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; ENABLED-NEXT: cmpl $2, %edx
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; ENABLED-NEXT: je .LBB2_3
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; ENABLED-NEXT: # %bb.1: # %entry
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; ENABLED-NEXT: cmpl $1, %edx
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; ENABLED-NEXT: jne .LBB2_4
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; ENABLED-NEXT: # %bb.2: # %sw.bb.1
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; ENABLED-NEXT: movl $111, (%rcx)
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; ENABLED-NEXT: movl $222, (%rax)
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; ENABLED-NEXT: retq
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; ENABLED-NEXT: .LBB2_3: # %sw.bb.2
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; ENABLED-NEXT: movl $333, (%rcx) # imm = 0x14D
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; ENABLED-NEXT: movl %eax, (%rax)
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; ENABLED-NEXT: .LBB2_4: # %sw.epilog
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; ENABLED-NEXT: retq
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;
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; DISABLED-LABEL: test3:
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; DISABLED: # %bb.0: # %entry
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; DISABLED-NEXT: movq %rdi, %rsi
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; DISABLED-NEXT: shlq $7, %rsi
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; DISABLED-NEXT: leaq arr2+132(%rsi,%rdi,8), %rcx
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; DISABLED-NEXT: leaq arr2(%rsi,%rdi,8), %rax
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; DISABLED-NEXT: movl arr2+132(%rsi,%rdi,8), %edx
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; DISABLED-NEXT: addl arr2(%rsi,%rdi,8), %edx
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; DISABLED-NEXT: cmpl $2, %edx
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; DISABLED-NEXT: je .LBB2_3
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; DISABLED-NEXT: # %bb.1: # %entry
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; DISABLED-NEXT: cmpl $1, %edx
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; DISABLED-NEXT: jne .LBB2_4
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; DISABLED-NEXT: # %bb.2: # %sw.bb.1
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; DISABLED-NEXT: movl $111, (%rcx)
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; DISABLED-NEXT: movl $222, (%rax)
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; DISABLED-NEXT: retq
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; DISABLED-NEXT: .LBB2_3: # %sw.bb.2
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; DISABLED-NEXT: movl $333, (%rcx) # imm = 0x14D
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; DISABLED-NEXT: movl %eax, (%rax)
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; DISABLED-NEXT: .LBB2_4: # %sw.epilog
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; DISABLED-NEXT: retq
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entry:
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%a = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 2
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon2], [65 x %struct.anon2]* @arr2, i64 0, i64 %x, i32 0
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%tmp1 = load i32, i32* %b, align 4
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%add = add nsw i32 %tmp, %tmp1
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %a, align 4
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store i32 222, i32* %b, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %a, align 4
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; Make sure the REG3's definition LEA won't be removed as redundant.
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%cvt = ptrtoint i32* %b to i32
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store i32 %cvt, i32* %b, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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; REG3's definition is closer to movl than REG2's, but the pass still chooses
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; REG2 because it provides the resultant address displacement fitting 1 byte.
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}
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define void @test4(i64 %x) nounwind minsize {
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; ENABLED-LABEL: test4:
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; ENABLED: # %bb.0: # %entry
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; ENABLED-NEXT: imulq $12, %rdi, %rax
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; ENABLED-NEXT: leaq arr1+4(%rax), %rax
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; ENABLED-NEXT: movl -4(%rax), %ecx
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; ENABLED-NEXT: subl (%rax), %ecx
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; ENABLED-NEXT: addl 4(%rax), %ecx
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; ENABLED-NEXT: cmpl $2, %ecx
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; ENABLED-NEXT: je .LBB3_3
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; ENABLED-NEXT: # %bb.1: # %entry
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; ENABLED-NEXT: cmpl $1, %ecx
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; ENABLED-NEXT: jne .LBB3_4
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; ENABLED-NEXT: # %bb.2: # %sw.bb.1
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; ENABLED-NEXT: movl $111, (%rax)
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; ENABLED-NEXT: movl $222, 4(%rax)
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; ENABLED-NEXT: retq
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; ENABLED-NEXT: .LBB3_3: # %sw.bb.2
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; ENABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; ENABLED-NEXT: movl $444, 4(%rax) # imm = 0x1BC
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; ENABLED-NEXT: .LBB3_4: # %sw.epilog
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; ENABLED-NEXT: retq
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;
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; DISABLED-LABEL: test4:
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; DISABLED: # %bb.0: # %entry
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; DISABLED-NEXT: imulq $12, %rdi, %rsi
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; DISABLED-NEXT: movl arr1(%rsi), %edx
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; DISABLED-NEXT: leaq arr1+4(%rsi), %rax
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; DISABLED-NEXT: subl arr1+4(%rsi), %edx
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; DISABLED-NEXT: leaq arr1+8(%rsi), %rcx
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; DISABLED-NEXT: addl arr1+8(%rsi), %edx
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; DISABLED-NEXT: cmpl $2, %edx
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; DISABLED-NEXT: je .LBB3_3
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; DISABLED-NEXT: # %bb.1: # %entry
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; DISABLED-NEXT: cmpl $1, %edx
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; DISABLED-NEXT: jne .LBB3_4
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; DISABLED-NEXT: # %bb.2: # %sw.bb.1
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; DISABLED-NEXT: movl $111, (%rax)
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; DISABLED-NEXT: movl $222, (%rcx)
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; DISABLED-NEXT: retq
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; DISABLED-NEXT: .LBB3_3: # %sw.bb.2
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; DISABLED-NEXT: movl $333, (%rax) # imm = 0x14D
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; DISABLED-NEXT: movl $444, (%rcx) # imm = 0x1BC
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; DISABLED-NEXT: .LBB3_4: # %sw.epilog
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; DISABLED-NEXT: retq
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entry:
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%a = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 0
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%tmp = load i32, i32* %a, align 4
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%b = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 1
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%tmp1 = load i32, i32* %b, align 4
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%sub = sub i32 %tmp, %tmp1
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%c = getelementptr inbounds [65 x %struct.anon1], [65 x %struct.anon1]* @arr1, i64 0, i64 %x, i32 2
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%tmp2 = load i32, i32* %c, align 4
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%add = add nsw i32 %sub, %tmp2
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switch i32 %add, label %sw.epilog [
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i32 1, label %sw.bb.1
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i32 2, label %sw.bb.2
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]
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sw.bb.1: ; preds = %entry
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store i32 111, i32* %b, align 4
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store i32 222, i32* %c, align 4
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br label %sw.epilog
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sw.bb.2: ; preds = %entry
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store i32 333, i32* %b, align 4
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store i32 444, i32* %c, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
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ret void
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}
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define i32 @test5(i32 %x, i32 %y) #0 {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: addl %esi, %esi
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: retq
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entry:
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%mul = mul nsw i32 %y, -2
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%add = add nsw i32 %mul, %x
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ret i32 %add
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}
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define i32 @test6(i32 %x, i32 %y) #0 {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: leal (%rsi,%rsi,2), %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: retq
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entry:
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%mul = mul nsw i32 %y, -3
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%add = add nsw i32 %mul, %x
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ret i32 %add
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}
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define i32 @test7(i32 %x, i32 %y) #0 {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll $2, %esi
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; CHECK-NEXT: subl %esi, %eax
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; CHECK-NEXT: retq
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entry:
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%mul = mul nsw i32 %y, -4
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%add = add nsw i32 %mul, %x
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ret i32 %add
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}
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define i32 @test8(i32 %x, i32 %y) #0 {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
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; CHECK-NEXT: leal (,%rsi,4), %eax
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; CHECK-NEXT: subl %edi, %eax
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; CHECK-NEXT: retq
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entry:
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%mul = shl nsw i32 %y, 2
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%sub = sub nsw i32 %mul, %x
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ret i32 %sub
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}
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define i32 @test9(i32 %x, i32 %y) #0 {
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; CHECK-LABEL: test9:
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; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: addl %esi, %esi
|
|
; CHECK-NEXT: subl %esi, %eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i32 -2, %y
|
|
%add = add nsw i32 %x, %mul
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @test10(i32 %x, i32 %y) #0 {
|
|
; CHECK-LABEL: test10:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: leal (%rsi,%rsi,2), %ecx
|
|
; CHECK-NEXT: subl %ecx, %eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i32 -3, %y
|
|
%add = add nsw i32 %x, %mul
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @test11(i32 %x, i32 %y) #0 {
|
|
; CHECK-LABEL: test11:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: shll $2, %esi
|
|
; CHECK-NEXT: subl %esi, %eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i32 -4, %y
|
|
%add = add nsw i32 %x, %mul
|
|
ret i32 %add
|
|
}
|
|
|
|
define i32 @test12(i32 %x, i32 %y) #0 {
|
|
; CHECK-LABEL: test12:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
|
|
; CHECK-NEXT: leal (,%rsi,4), %eax
|
|
; CHECK-NEXT: subl %edi, %eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i32 4, %y
|
|
%sub = sub nsw i32 %mul, %x
|
|
ret i32 %sub
|
|
}
|
|
|
|
define i64 @test13(i64 %x, i64 %y) #0 {
|
|
; CHECK-LABEL: test13:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: movq %rdi, %rax
|
|
; CHECK-NEXT: shlq $2, %rsi
|
|
; CHECK-NEXT: subq %rsi, %rax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i64 -4, %y
|
|
%add = add nsw i64 %x, %mul
|
|
ret i64 %add
|
|
}
|
|
|
|
define i32 @test14(i32 %x, i32 %y) #0 {
|
|
; CHECK-LABEL: test14:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
|
|
; CHECK-NEXT: leal (,%rsi,4), %eax
|
|
; CHECK-NEXT: subl %edi, %eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%mul = mul nsw i32 4, %y
|
|
%sub = sub nsw i32 %mul, %x
|
|
ret i32 %sub
|
|
}
|
|
|
|
define zeroext i16 @test15(i16 zeroext %x, i16 zeroext %y) #0 {
|
|
; CHECK-LABEL: test15:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: movl %edi, %eax
|
|
; CHECK-NEXT: shll $3, %esi
|
|
; CHECK-NEXT: subl %esi, %eax
|
|
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
|
|
; CHECK-NEXT: retq
|
|
entry:
|
|
%conv = zext i16 %x to i32
|
|
%conv1 = zext i16 %y to i32
|
|
%mul = mul nsw i32 -8, %conv1
|
|
%add = add nsw i32 %conv, %mul
|
|
%conv2 = trunc i32 %add to i16
|
|
ret i16 %conv2
|
|
}
|
|
|
|
attributes #0 = { norecurse nounwind optsize readnone uwtable}
|