forked from OSchip/llvm-project
291 lines
7.3 KiB
YAML
291 lines
7.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define signext i8 @float_to_int8(float %val) {
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entry:
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%conv = fptosi float %val to i8
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ret i8 %conv
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}
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define signext i16 @float_to_int16(float %val) {
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entry:
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%conv = fptosi float %val to i16
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ret i16 %conv
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}
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define i32 @float_to_int32(float %val) {
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entry:
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%conv = fptosi float %val to i32
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ret i32 %conv
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}
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define i64 @float_to_int64(float %val) {
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entry:
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%conv = fptosi float %val to i64
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ret i64 %conv
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}
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define signext i8 @double_to_int8(double %val) {
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entry:
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%conv = fptosi double %val to i8
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ret i8 %conv
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}
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define signext i16 @double_to_int16(double %val) {
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entry:
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%conv = fptosi double %val to i16
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ret i16 %conv
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}
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define i32 @double_to_int32(double %val) {
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entry:
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%conv = fptosi double %val to i32
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ret i32 %conv
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}
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define i64 @double_to_int64(double %val) {
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entry:
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%conv = fptosi double %val to i64
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ret i64 %conv
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}
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...
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---
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name: float_to_int8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: float_to_int8
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
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; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSS2SIrr]].sub_8bit
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; CHECK: $al = COPY [[COPY2]]
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; CHECK: RET 0, implicit $al
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s32) = G_TRUNC %1(s128)
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%3:gpr(s32) = G_FPTOSI %0(s32)
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%2:gpr(s8) = G_TRUNC %3(s32)
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: float_to_int16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: float_to_int16
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
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; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSS2SIrr]].sub_16bit
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; CHECK: $ax = COPY [[COPY2]]
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; CHECK: RET 0, implicit $ax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s32) = G_TRUNC %1(s128)
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%3:gpr(s32) = G_FPTOSI %0(s32)
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%2:gpr(s16) = G_TRUNC %3(s32)
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: float_to_int32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: float_to_int32
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; CHECK: [[CVTTSS2SIrr:%[0-9]+]]:gr32 = CVTTSS2SIrr [[COPY1]]
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; CHECK: $eax = COPY [[CVTTSS2SIrr]]
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; CHECK: RET 0, implicit $eax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s32) = G_TRUNC %1(s128)
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%2:gpr(s32) = G_FPTOSI %0(s32)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: float_to_int64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: float_to_int64
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr32 = COPY [[COPY]]
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; CHECK: [[CVTTSS2SI64rr:%[0-9]+]]:gr64 = CVTTSS2SI64rr [[COPY1]]
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; CHECK: $rax = COPY [[CVTTSS2SI64rr]]
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; CHECK: RET 0, implicit $rax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s32) = G_TRUNC %1(s128)
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%2:gpr(s64) = G_FPTOSI %0(s32)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: double_to_int8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: double_to_int8
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
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; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[CVTTSD2SIrr]].sub_8bit
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; CHECK: $al = COPY [[COPY2]]
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; CHECK: RET 0, implicit $al
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s64) = G_TRUNC %1(s128)
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%3:gpr(s32) = G_FPTOSI %0(s64)
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%2:gpr(s8) = G_TRUNC %3(s32)
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: double_to_int16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: double_to_int16
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
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; CHECK: [[COPY2:%[0-9]+]]:gr16 = COPY [[CVTTSD2SIrr]].sub_16bit
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; CHECK: $ax = COPY [[COPY2]]
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; CHECK: RET 0, implicit $ax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s64) = G_TRUNC %1(s128)
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%3:gpr(s32) = G_FPTOSI %0(s64)
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%2:gpr(s16) = G_TRUNC %3(s32)
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: double_to_int32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: double_to_int32
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; CHECK: [[CVTTSD2SIrr:%[0-9]+]]:gr32 = CVTTSD2SIrr [[COPY1]]
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; CHECK: $eax = COPY [[CVTTSD2SIrr]]
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; CHECK: RET 0, implicit $eax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s64) = G_TRUNC %1(s128)
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%2:gpr(s32) = G_FPTOSI %0(s64)
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: double_to_int64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vecr }
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- { id: 1, class: vecr }
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- { id: 2, class: gpr }
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body: |
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bb.1.entry:
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liveins: $xmm0
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; CHECK-LABEL: name: double_to_int64
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; CHECK: liveins: $xmm0
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; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
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; CHECK: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
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; CHECK: [[CVTTSD2SI64rr:%[0-9]+]]:gr64 = CVTTSD2SI64rr [[COPY1]]
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; CHECK: $rax = COPY [[CVTTSD2SI64rr]]
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; CHECK: RET 0, implicit $rax
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%1:vecr(s128) = COPY $xmm0
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%0:vecr(s64) = G_TRUNC %1(s128)
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%2:gpr(s64) = G_FPTOSI %0(s64)
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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