forked from OSchip/llvm-project
146 lines
3.6 KiB
YAML
146 lines
3.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
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--- |
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define i8 @test_and_i8(i8 %arg1, i8 %arg2) {
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%ret = and i8 %arg1, %arg2
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ret i8 %ret
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}
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define i16 @test_and_i16(i16 %arg1, i16 %arg2) {
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%ret = and i16 %arg1, %arg2
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ret i16 %ret
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}
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define i32 @test_and_i32(i32 %arg1, i32 %arg2) {
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%ret = and i32 %arg1, %arg2
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ret i32 %ret
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}
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define i64 @test_and_i64(i64 %arg1, i64 %arg2) {
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%ret = and i64 %arg1, %arg2
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ret i64 %ret
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}
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...
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---
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name: test_and_i8
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; ALL-LABEL: name: test_and_i8
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; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil
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; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
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; ALL: [[AND8rr:%[0-9]+]]:gr8 = AND8rr [[COPY]], [[COPY1]], implicit-def $eflags
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; ALL: $al = COPY [[AND8rr]]
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; ALL: RET 0, implicit $al
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%0(s8) = COPY $dil
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%1(s8) = COPY $sil
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%2(s8) = G_AND %0, %1
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: test_and_i16
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; ALL-LABEL: name: test_and_i16
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; ALL: [[COPY:%[0-9]+]]:gr16 = COPY $di
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; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY $si
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; ALL: [[AND16rr:%[0-9]+]]:gr16 = AND16rr [[COPY]], [[COPY1]], implicit-def $eflags
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; ALL: $ax = COPY [[AND16rr]]
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; ALL: RET 0, implicit $ax
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%0(s16) = COPY $di
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%1(s16) = COPY $si
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%2(s16) = G_AND %0, %1
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: test_and_i32
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; ALL-LABEL: name: test_and_i32
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; ALL: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
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; ALL: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[COPY]], [[COPY1]], implicit-def $eflags
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; ALL: $eax = COPY [[AND32rr]]
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; ALL: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = G_AND %0, %1
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_and_i64
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alignment: 4
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gpr, preferred-register: '' }
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liveins:
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fixedStack:
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stack:
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constants:
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; ALL-LABEL: name: test_and_i64
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; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
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; ALL: [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[COPY]], [[COPY1]], implicit-def $eflags
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; ALL: $rax = COPY [[AND64rr]]
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; ALL: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_AND %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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