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llvm-project/llvm/test/CodeGen/RISCV
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Alex Bradbury 919f5fb8ca [RISCV] Add support for the various RISC-V FMA instruction variants 
Adds support for the various RISC-V FMA instructions (fmadd, fmsub, fnmsub, fnmadd).

The criteria for choosing whether a fused add or subtract is used, as well as
whether the product is negated or not, is whether some of the arguments to the
llvm.fma.* intrinsic are negated or not. In the tests, extraneous fadd
instructions were added to avoid the negation being performed using a xor
trick, which prevented the proper FMA forms from being selected and thus
tested.

The FMA instruction patterns might seem incorrect (e.g., fnmadd: -rs1 * rs2 -
rs3), but they should be correct. The misleading names were inherited from
MIPS, where the negation happens after computing the sum.

The llvm.fmuladd.* intrinsics still do not generate RISC-V FMA instructions,
as that depends on TargetLowering::isFMAFasterthanFMulAndFAdd.

Some comments in the test files about what type of instructions are there
tested were updated, to better reflect the current content of those test
files.

Differential Revision: https://reviews.llvm.org/D54205
Patch by Luís Marques.

llvm-svn: 349023
 		2018-12-13 10:49:05 +00:00
..
addc-adde-sube-subc.ll
…
align.ll [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC 2018-04-12 11:30:59 +00:00
alloca.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
alu8.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu16.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
alu32.ll [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
alu64.ll [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 2018-12-01 05:00:00 +00:00
analyze-branch.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
arith-with-overflow.ll [RISCV] Add tests for overflow intrinsics 2018-06-19 06:45:47 +00:00
atomic-cmpxchg.ll [RISCV] Implement codegen for cmpxchg on RV32IA 2018-11-29 20:43:42 +00:00
atomic-fence.ll [RISCV] Codegen support for atomic operations on RV32I 2018-06-13 11:58:46 +00:00
atomic-load-store.ll [RISCV] atomic_store_nn have a different layout to regular store 2018-08-27 07:08:18 +00:00
atomic-rmw.ll [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A 2018-09-19 10:54:22 +00:00
bare-select.ll
…
blockaddress.ll
…
branch-relaxation.ll
…
branch.ll [RISCV] Expand codegen -> compression sanity checks and move to a single file 2018-04-18 20:17:29 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Set CostPerUse for registers 2018-05-23 21:34:30 +00:00
byval.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
calling-conv-rv32f-ilp32.ll [RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F 2018-10-04 07:28:49 +00:00
calling-conv-sext-zext.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
calling-conv.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
calls.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
compress-inline-asm.ll
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compress.ll [RISCV] Add test changes missed from rL330293 2018-04-18 20:36:12 +00:00
disable-tail-calls.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
div.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-arith.ll [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
double-br-fcmp.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-calling-conv.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-convert.ll [RISCV] Codegen support for RV32D floating point conversion operations 2018-04-12 05:47:15 +00:00
double-fcmp.ll [RISCV] Codegen support for RV32D floating point comparison operations 2018-04-12 05:50:06 +00:00
double-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
double-imm.ll
…
double-intrinsics.ll [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
double-mem.ll [RISCV] Set CostPerUse for registers 2018-05-23 21:34:30 +00:00
double-previous-failure.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-select-fcmp.ll [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default 2018-10-05 18:25:55 +00:00
double-stack-spill-restore.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
fixups-diff.ll [RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true 2018-08-16 11:26:37 +00:00
fixups-relax-diff.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
float-arith.ll [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
float-br-fcmp.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
float-convert.ll
…
float-fcmp.ll
…
float-frem.ll [RISCV] Mark FREM as Expand 2018-11-15 14:46:11 +00:00
float-imm.ll
…
float-intrinsics.ll [RISCV] Add support for the various RISC-V FMA instruction variants 2018-12-13 10:49:05 +00:00
float-mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
float-select-fcmp.ll
…
flt-rounds.ll [SelectionDAG] Support result type promotion for FLT_ROUNDS_ 2018-11-30 13:18:33 +00:00
fp128.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
frame.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
frameaddr-returnaddr.ll [SelectionDAG] Support promotion of FRAMEADDR/RETURNADDR operands 2018-11-30 10:02:06 +00:00
get-setcc-result-type.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
hoist-global-addr-base.ll [RISCV] Add machine function pass to merge base + offset 2018-06-27 20:51:42 +00:00
i32-icmp.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
imm-cse.ll [RISCV] Add imm-cse.ll test case 2018-04-18 20:25:07 +00:00
imm.ll [RISCV] Constant materialisation for RV64I 2018-11-16 10:14:16 +00:00
indirectbr.ll [RISC-V] Fix a test case to not include label names as those aren't 2018-06-21 05:42:05 +00:00
init-array.ll
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inline-asm.ll
…
interrupt-attr-args-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr-ret-error.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
interrupt-attr.ll [RISCV] Add support for _interrupt attribute 2018-07-26 17:49:43 +00:00
jumptable.ll
…
large-stack.ll
…
lit.local.cfg
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lsr-legaladdimm.ll [RISCV] Implement isLegalAddImmediate 2018-04-26 13:00:37 +00:00
mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
mem64.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
mul.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
musttail-call.ll [RISCV] Lower the tail pseudoinstruction 2018-05-23 22:44:08 +00:00
option-norelax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-norvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
option-relax.ll [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
option-rvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
prefetch.ll [SelectionDAG] Support promotion of PREFETCH operands 2018-11-30 10:06:31 +00:00
rem.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
remat.ll [RISCV] Set CostPerUse for registers 2018-05-23 21:34:30 +00:00
rotl-rotr.ll
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rv64i-exhaustive-w-insts.ll [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 2018-12-01 05:00:00 +00:00
rv64i-tricky-shifts.ll [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test cases 2018-12-01 05:00:00 +00:00
select-cc.ll
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sext-zext-trunc.ll [RISCV] Introduce codegen patterns for instructions introduced in RV64I 2018-11-30 09:38:44 +00:00
shift-masked-shamt.ll [RISCV] Eliminate unnecessary masking of promoted shift amounts 2018-10-12 23:18:52 +00:00
shifts.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
tail-calls.ll [RISCV] Fixed test case failure due to r338047 2018-07-31 00:36:28 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Avoid unnecessary XOR for seteq/setne 0 2018-11-09 14:47:36 +00:00
vararg.ll [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142 2018-10-11 11:11:58 +00:00
wide-mem.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00
zext-with-load-is-free.ll [RISCV] Separate base from offset in lowerGlobalAddress 2018-05-17 18:14:53 +00:00