forked from OSchip/llvm-project
223 lines
8.0 KiB
LLVM
223 lines
8.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_on:
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; GCN: v_mul_f32_e64 [[QUIET0:v[0-9]+]], 1.0, s{{[0-9]+}}
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; GCN: v_mul_f32_e64 [[QUIET1:v[0-9]+]], 1.0, s{{[0-9]+}}
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; GCN: v_max_f32_e32 [[RESULT:v[0-9]+]], [[QUIET1]], [[QUIET0]]
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; GCN-NOT: [[RESULT]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_fmax_f32_ieee_mode_on(float addrspace(1)* %out, float %a, float %b) #0 {
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%val = call float @llvm.maxnum.f32(float %a, float %b) #1
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_off:
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; GCN: v_max_f32_e32 v0, v0, v1
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; GCN-NEXT: ; return
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define amdgpu_ps float @test_fmax_f32_ieee_mode_off(float %a, float %b) #0 {
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%val = call float @llvm.maxnum.f32(float %a, float %b) #1
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ret float %val
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}
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; GCN-LABEL: {{^}}test_fmax_v2f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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define amdgpu_kernel void @test_fmax_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) #0 {
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%val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
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store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax_v3f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN-NOT: v_max_f32
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define amdgpu_kernel void @test_fmax_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, <3 x float> %b) nounwind {
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%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b) #0
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store <3 x float> %val, <3 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax_v4f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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define amdgpu_kernel void @test_fmax_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) #0 {
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%val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
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store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax_v8f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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define amdgpu_kernel void @test_fmax_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) #0 {
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%val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b)
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store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32
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ret void
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}
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; GCN-LABEL: {{^}}test_fmax_v16f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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define amdgpu_kernel void @test_fmax_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) #0 {
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%val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b)
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store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 1.0, float 2.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_nan:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_val_nan:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_val:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_p0:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 0.0, float 0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_n0:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float 0.0, float -0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_p0:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float -0.0, float 0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_n0:
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; GCN-NOT: v_max_f32_e32
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; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
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; GCN: buffer_store_dword [[REG]]
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define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(float addrspace(1)* %out) #0 {
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%val = call float @llvm.maxnum.f32(float -0.0, float -0.0)
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}fmax_var_immediate_f32_no_ieee:
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; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
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define amdgpu_ps float @fmax_var_immediate_f32_no_ieee(float inreg %a) #0 {
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%val = call float @llvm.maxnum.f32(float %a, float 2.0) #0
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ret float %val
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}
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; GCN-LABEL: {{^}}fmax_immediate_var_f32_no_ieee:
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; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
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define amdgpu_ps float @fmax_immediate_var_f32_no_ieee(float inreg %a) #0 {
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%val = call float @llvm.maxnum.f32(float 2.0, float %a) #0
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ret float %val
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}
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; GCN-LABEL: {{^}}fmax_var_literal_f32_no_ieee:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
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; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
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define amdgpu_ps float @fmax_var_literal_f32_no_ieee(float inreg %a) #0 {
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%val = call float @llvm.maxnum.f32(float %a, float 99.0) #0
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ret float %val
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}
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; GCN-LABEL: {{^}}fmax_literal_var_f32_no_ieee:
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; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
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; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
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define amdgpu_ps float @fmax_literal_var_f32_no_ieee(float inreg %a) #0 {
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%val = call float @llvm.maxnum.f32(float 99.0, float %a) #0
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ret float %val
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}
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; GCN-LABEL: {{^}}test_func_fmax_v3f32:
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN: v_max_f32_e32
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; GCN-NOT: v_max_f32
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define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) nounwind {
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%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b) #0
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ret <3 x float> %val
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}
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declare float @llvm.maxnum.f32(float, float) #1
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declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1
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declare <3 x float> @llvm.maxnum.v3f32(<3 x float>, <3 x float>) #1
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declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
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declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1
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declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1
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declare double @llvm.maxnum.f64(double, double)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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