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AArch64
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Initial AArch64 SLH implementation.
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2019-01-09 15:13:34 +00:00 |
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AMDGPU
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Revert "[AMDGPU] Fix DPP combiner"
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2019-01-09 15:21:53 +00:00 |
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ARC
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…
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ARM
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[ARM] Add missing patterns for DSP muls
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2019-01-08 10:12:36 +00:00 |
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AVR
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[AVR] Update integration/blink.ll as we now generate sbi/cbi instructions.
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2019-01-03 21:25:39 +00:00 |
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BPF
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[BPF] Fix .BTF.ext reloc type assigment issue
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2019-01-08 16:36:06 +00:00 |
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Generic
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Move llc-start-stop-instance to x86
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2018-12-04 18:19:08 +00:00 |
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Hexagon
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[DAGCombiner] allow narrowing of add followed by truncate
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2018-12-22 17:10:31 +00:00 |
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Inputs
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…
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Lanai
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[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
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2018-12-07 12:10:23 +00:00 |
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MIR
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[Dwarf/AArch64] Return address signing B key dwarf support
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2018-12-21 10:45:08 +00:00 |
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MSP430
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[MSP430] Optimize 'shl x, 8[+ N] -> swpb(zext(x)) [<< N]' for i16
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2019-01-09 13:03:01 +00:00 |
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Mips
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[MIPS GlobalISel] Select G_SELECT
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2018-12-25 14:42:30 +00:00 |
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NVPTX
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Python compat - print statement
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2019-01-03 14:11:33 +00:00 |
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Nios2
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…
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PowerPC
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Revert "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
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2019-01-09 06:12:24 +00:00 |
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RISCV
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[RISCV] Add support for the various RISC-V FMA instruction variants
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2018-12-13 10:49:05 +00:00 |
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SPARC
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[Sparc] Use float register for integer constrained with "f" in inline asm
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2018-12-13 15:13:29 +00:00 |
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SystemZ
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Pythran compat - range vs. xrange
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2019-01-03 14:11:58 +00:00 |
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Thumb
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[ARM] Complete the Thumb1 shift+and->shift+shift transforms.
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2018-12-20 23:39:54 +00:00 |
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Thumb2
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[ARM] Enable spilling of the hGPR register class in Thumb2
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2018-11-08 13:02:10 +00:00 |
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WebAssembly
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Fix typo in comment
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2019-01-09 14:20:20 +00:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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[x86] use 'nounwind' to remove test noise; NFC
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2019-01-09 17:29:18 +00:00 |
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XCore
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[Targets] Add errors for tiny and kernel codemodel on targets that don't support them
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2018-12-07 12:10:23 +00:00 |
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