forked from OSchip/llvm-project
188 lines
9.4 KiB
TableGen
188 lines
9.4 KiB
TableGen
// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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def SelectClamp : ComplexPattern<untyped, 2, "SelectClamp">;
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def SelectOMod : ComplexPattern<untyped, 2, "SelectOMod">;
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def SelectClampOMod : ComplexPattern<untyped, 3, "SelectClampOMod">;
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def SelectSrcMods : ComplexPattern<untyped, 2, "SelectSrcMods">;
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def gi_SelectClamp :
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GIComplexOperandMatcher<s32, "selectClamp">,
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GIComplexPatternEquiv<SelectClamp>;
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def gi_SelectOMod :
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GIComplexOperandMatcher<s32, "selectOMod">,
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GIComplexPatternEquiv<SelectOMod>;
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def gi_SelectClampOMod :
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GIComplexOperandMatcher<s32, "selectClampOMod">,
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GIComplexPatternEquiv<SelectClampOMod>;
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def gi_SelectSrcMods :
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GIComplexOperandMatcher<s32, "selectSrcMods">,
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GIComplexPatternEquiv<SelectSrcMods>;
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def src_mods : Operand <i32>;
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def omod : OperandWithDefaultOps <i32, (ops (i32 0))>;
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def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>;
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMAXNUM,
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// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectSrcMods,
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// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_SelectSrcMods,
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// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods0
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // mods1
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FFLOOR,
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// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectClampOMod,
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// CHECK: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLOMP,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCANONICALIZE,
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// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCOS,
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// CHECK: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FEXP2,
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// CHECK: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp)
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// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::FFOO,
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/0,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FEEPLE,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSIN,
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// CHECK: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSQRT,
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// CHECK: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/93,
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// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_ROUND,
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// CHECK: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FBAR,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_TRUNC,
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// CHECK: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO,
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
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// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0,
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// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// Have default operand with explicit value from complex pattern.
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def FFOO : I<(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp),
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[(set FPR32:$dst, (fsin (SelectClamp f32:$src0, i1:$clamp)))]>;
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// Have default operand, not explicitly specified in a standalone
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// pattern.
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def : Pat <
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(ftrunc f32:$src0),
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(FFOO FPR32:$src0)
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>;
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// Have default operand, not explicitly specified in an instruction
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// definition pattern.
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def FBAR : I<(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp),
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[(set FPR32:$dst, (fround f32:$src0))]>;
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// // Swapped order in instruction from pattern
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def FLOMP : I<
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(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp, omod:$omod),
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[(set FPR32:$dst, (ffloor (SelectClampOMod f32:$src0, omod:$omod, i1:$clamp)))]>;
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def FLAMP : I<(outs FPR32:$dst), (ins FPR32:$src0, omod:$omod, clamp:$clamp), []>;
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// // Have 2 default operands, and the first is specified
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def : Pat <
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(fcos (SelectOMod f32:$src0, i32:$omod)),
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(FLAMP FPR32:$src0, omod:$omod)
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>;
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// Immediate used for first defaulted operand
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def : Pat <
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(fsqrt (SelectClamp f32:$src0, i1:$clamp)),
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(FLAMP FPR32:$src0, 93, clamp:$clamp)
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>;
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def FEEPLE : I<(outs FPR32:$dst),
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(ins FPR32:$src0, FPR32:$src1, clamp:$clamp), []>;
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// Default operand isn't on the root ouput instruction
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def : Pat <
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(fexp2 (SelectClamp f32:$src0, i1:$clamp)),
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(FEEPLE FPR32:$src0, (FFOO FPR32:$src0), clamp:$clamp)
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>;
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// Same instruction is used in two different pattern contexts, one
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// uses the default and one does not.
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def FMAX : I<(outs FPR32:$dst),
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(ins src_mods:$mods0, FPR32:$src0, src_mods:$mods1, FPR32:$src1, clamp:$clamp),
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[(set FPR32:$dst, (f32 (fmaxnum (SelectSrcMods f32:$src0, src_mods:$mods0),
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(SelectSrcMods f32:$src1, src_mods:$mods1))))]
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>;
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def : Pat<
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(fcanonicalize (f32 (SelectSrcMods f32:$src, i32:$mods))),
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(FMAX $mods, $src, $mods, $src, 0)
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>;
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