forked from OSchip/llvm-project
39 lines
934 B
TableGen
39 lines
934 B
TableGen
// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def R0 : Register<"r0">;
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def Reg : RegisterClass<"Reg", [i32], 0, (add R0)>;
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def IntOperand: Operand<i32>;
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def PCRelOperand : Operand<i32> {
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let OperandType = "OPERAND_PCREL";
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}
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def foo : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins Reg:$reg, IntOperand:$imm);
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let AsmString = "foo $reg, $imm";
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}
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def bar : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins Reg:$reg, PCRelOperand:$imm);
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let AsmString = "bar $reg, $imm";
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}
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// CHECK: ArchInstPrinter::printInstruction(
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// CHECK: // bar, foo
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// CHECK-NEXT: printOperand(MI, 0, O);
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// CHECK: // foo
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// CHECK-NEXT: printOperand(MI, 1, O);
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// CHECK: // bar
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// CHECK-NEXT: printOperand(MI, Address, 1, O);
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