forked from OSchip/llvm-project
85 lines
3.1 KiB
LLVM
85 lines
3.1 KiB
LLVM
; RUN: opt < %s -jump-threading -print-lazy-value-info -disable-output 2>&1 | FileCheck %s
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; Testing LVI cache after jump-threading
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; Jump-threading transforms the IR below to one where
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; loop and backedge basic blocks are merged into one.
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; basic block (named backedge) with the branch being:
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; %cont = icmp slt i32 %iv.next, 400
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; br i1 %cont, label %backedge, label %exit
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define i8 @test1(i32 %a, i32 %length) {
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; CHECK-LABEL: LVI for function 'test1':
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entry:
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br label %loop
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; CHECK-LABEL: backedge:
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; CHECK-NEXT: ; CachedLatticeValues for: ' %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]'
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; CHECK-DAG: ; at beginning of BasicBlock: '%backedge' LatticeVal: 'constantrange<0, 400>'
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; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]
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; CHECK-NEXT: ; CachedLatticeValues for: ' %iv.next = add nsw i32 %iv, 1'
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; CHECK-NEXT: ; at beginning of BasicBlock: '%backedge' LatticeVal: 'constantrange<1, 401>'
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; CHECK-NEXT: %iv.next = add nsw i32 %iv, 1
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; CHECK-NEXT: %cont = icmp slt i32 %iv.next, 400
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; CHECK-NEXT: br i1 %cont, label %backedge, label %exit
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; CHECK-NOT: loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%cnd = icmp sge i32 %iv, 0
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br i1 %cnd, label %backedge, label %exit
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backedge:
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%iv.next = add nsw i32 %iv, 1
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%cont = icmp slt i32 %iv.next, 400
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br i1 %cont, label %loop, label %exit
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exit:
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ret i8 0
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}
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; Here JT does not transform the code, but LVICache is populated during the processing of blocks.
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define i8 @test2(i32 %n) {
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; CHECK-LABEL: LVI for function 'test2':
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; CHECK-LABEL: entry:
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; CHECK-LABEL: ; OverDefined values for block are:
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; CHECK-NEXT: ;i32 %n
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; CHECK-NEXT: br label %loop
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entry:
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br label %loop
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; CHECK-LABEL: loop:
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; CHECK-LABEL: ; OverDefined values for block are:
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; CHECK-NEXT: ; %iv2 = phi i32 [ %n, %entry ], [ %iv2.next, %backedge ]
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; CHECK-NEXT: ; CachedLatticeValues for: ' %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]'
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; CHECK-DAG: ; at beginning of BasicBlock: '%loop' LatticeVal: 'constantrange<0, -2147483647>'
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; CHECK-DAG: ; at beginning of BasicBlock: '%backedge' LatticeVal: 'constantrange<0, -2147483648>'
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; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ]
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; CHECK: %cnd = and i1 %cnd1, %cnd2
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; CHECK: br i1 %cnd, label %backedge, label %exit
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%iv2 = phi i32 [%n, %entry], [%iv2.next, %backedge]
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%cnd1 = icmp sge i32 %iv, 0
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%cnd2 = icmp sgt i32 %iv2, 0
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%cnd = and i1 %cnd1, %cnd2
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br i1 %cnd, label %backedge, label %exit
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; CHECK-LABEL: backedge:
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; CHECK-NEXT: ; CachedLatticeValues for: ' %iv.next = add nsw i32 %iv, 1'
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; CHECK-NEXT: ; at beginning of BasicBlock: '%backedge' LatticeVal: 'constantrange<1, -2147483647>'
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; CHECK-NEXT: %iv.next = add nsw i32 %iv, 1
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; CHECK-NEXT: %iv2.next = sub nsw i32 %iv2, 1
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; CHECK: %cont = and i1 %cont1, %cont2
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; CHECK: br i1 %cont, label %loop, label %exit
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backedge:
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%iv.next = add nsw i32 %iv, 1
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%iv2.next = sub nsw i32 %iv2, 1
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%cont1 = icmp slt i32 %iv.next, 400
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%cont2 = icmp sgt i32 %iv2.next, 0
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%cont = and i1 %cont1, %cont2
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br i1 %cont, label %loop, label %exit
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exit:
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ret i8 0
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}
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