forked from OSchip/llvm-project
1ee6ce9bad
SelectionDAG has a target hook, getExtendForAtomicOps, which it uses in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty ugly (as is having a separate load opcode for atomics), so instead allow making use of atomic zextload. Enable this for AArch64 since the DAG path defaults in to the zext behavior. The tablegen changes are pretty ugly, but partially helps migrate SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with atomic memory operands. For now the DAG emitter will emit matchers for patterns which the DAG will not produce. I'm still a bit confused by the intent of the isLoad/isStore/isAtomic bits. The DAG implementation rejects trying to use any of these in combination. For now I've opted to make the isLoad checks also check isAtomic, although I think having isLoad and isAtomic set on these makes most sense. |
||
|---|---|---|
| .. | ||
| GMIR.rst | ||
| GenericOpcode.rst | ||
| IRTranslator.rst | ||
| InstructionSelect.rst | ||
| KnownBits.rst | ||
| Legalizer.rst | ||
| Pipeline.rst | ||
| Porting.rst | ||
| RegBankSelect.rst | ||
| Resources.rst | ||
| block-extract.png | ||
| index.rst | ||
| pipeline-overview-customized.png | ||
| pipeline-overview-with-combiners.png | ||
| pipeline-overview.png | ||
| testing-pass-level.png | ||
| testing-unit-level.png | ||
