forked from OSchip/llvm-project
300 lines
11 KiB
C++
300 lines
11 KiB
C++
//===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file implements the LegalizerHelper class to legalize individual
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/// instructions and the LegalizePass wrapper pass for the primary
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/// legalization.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/Legalizer.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
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#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
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#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetMachine.h"
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#include <iterator>
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#define DEBUG_TYPE "legalizer"
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using namespace llvm;
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static cl::opt<bool>
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EnableCSEInLegalizer("enable-cse-in-legalizer",
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cl::desc("Should enable CSE in Legalizer"),
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cl::Optional, cl::init(false));
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char Legalizer::ID = 0;
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INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
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INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
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INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
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"Legalize the Machine IR a function's Machine IR", false,
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false)
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Legalizer::Legalizer() : MachineFunctionPass(ID) { }
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void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.addRequired<GISelCSEAnalysisWrapperPass>();
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AU.addPreserved<GISelCSEAnalysisWrapperPass>();
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getSelectionDAGFallbackAnalysisUsage(AU);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void Legalizer::init(MachineFunction &MF) {
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}
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static bool isArtifact(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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default:
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return false;
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case TargetOpcode::G_TRUNC:
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case TargetOpcode::G_ZEXT:
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case TargetOpcode::G_ANYEXT:
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case TargetOpcode::G_SEXT:
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case TargetOpcode::G_MERGE_VALUES:
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case TargetOpcode::G_UNMERGE_VALUES:
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case TargetOpcode::G_CONCAT_VECTORS:
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case TargetOpcode::G_BUILD_VECTOR:
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case TargetOpcode::G_EXTRACT:
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return true;
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}
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}
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using InstListTy = GISelWorkList<256>;
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using ArtifactListTy = GISelWorkList<128>;
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namespace {
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class LegalizerWorkListManager : public GISelChangeObserver {
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InstListTy &InstList;
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ArtifactListTy &ArtifactList;
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#ifndef NDEBUG
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SmallVector<MachineInstr *, 4> NewMIs;
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#endif
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public:
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LegalizerWorkListManager(InstListTy &Insts, ArtifactListTy &Arts)
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: InstList(Insts), ArtifactList(Arts) {}
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void createdOrChangedInstr(MachineInstr &MI) {
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// Only legalize pre-isel generic instructions.
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// Legalization process could generate Target specific pseudo
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// instructions with generic types. Don't record them
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if (isPreISelGenericOpcode(MI.getOpcode())) {
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if (isArtifact(MI))
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ArtifactList.insert(&MI);
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else
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InstList.insert(&MI);
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}
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}
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void createdInstr(MachineInstr &MI) override {
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LLVM_DEBUG(dbgs() << ".. .. New MI: " << MI);
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LLVM_DEBUG(NewMIs.push_back(&MI));
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createdOrChangedInstr(MI);
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}
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void printNewInstrs() {
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LLVM_DEBUG({
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for (const auto *MI : NewMIs)
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dbgs() << ".. .. New MI: " << *MI;
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NewMIs.clear();
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});
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}
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void erasingInstr(MachineInstr &MI) override {
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LLVM_DEBUG(dbgs() << ".. .. Erasing: " << MI);
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InstList.remove(&MI);
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ArtifactList.remove(&MI);
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}
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void changingInstr(MachineInstr &MI) override {
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LLVM_DEBUG(dbgs() << ".. .. Changing MI: " << MI);
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}
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void changedInstr(MachineInstr &MI) override {
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// When insts change, we want to revisit them to legalize them again.
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// We'll consider them the same as created.
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LLVM_DEBUG(dbgs() << ".. .. Changed MI: " << MI);
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createdOrChangedInstr(MI);
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}
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};
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} // namespace
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bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
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init(MF);
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const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
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GISelCSEAnalysisWrapper &Wrapper =
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getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
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MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
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const size_t NumBlocks = MF.size();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Populate Insts
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InstListTy InstList;
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ArtifactListTy ArtifactList;
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ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
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// Perform legalization bottom up so we can DCE as we legalize.
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// Traverse BB in RPOT and within each basic block, add insts top down,
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// so when we pop_back_val in the legalization process, we traverse bottom-up.
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for (auto *MBB : RPOT) {
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if (MBB->empty())
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continue;
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for (MachineInstr &MI : *MBB) {
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// Only legalize pre-isel generic instructions: others don't have types
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// and are assumed to be legal.
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if (!isPreISelGenericOpcode(MI.getOpcode()))
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continue;
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if (isArtifact(MI))
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ArtifactList.deferred_insert(&MI);
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else
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InstList.deferred_insert(&MI);
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}
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}
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ArtifactList.finalize();
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InstList.finalize();
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std::unique_ptr<MachineIRBuilder> MIRBuilder;
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GISelCSEInfo *CSEInfo = nullptr;
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bool EnableCSE = EnableCSEInLegalizer.getNumOccurrences()
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? EnableCSEInLegalizer
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: TPC.isGISelCSEEnabled();
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if (EnableCSE) {
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MIRBuilder = std::make_unique<CSEMIRBuilder>();
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CSEInfo = &Wrapper.get(TPC.getCSEConfig());
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MIRBuilder->setCSEInfo(CSEInfo);
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} else
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MIRBuilder = std::make_unique<MachineIRBuilder>();
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// This observer keeps the worklist updated.
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LegalizerWorkListManager WorkListObserver(InstList, ArtifactList);
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// We want both WorkListObserver as well as CSEInfo to observe all changes.
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// Use the wrapper observer.
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GISelObserverWrapper WrapperObserver(&WorkListObserver);
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if (EnableCSE && CSEInfo)
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WrapperObserver.addObserver(CSEInfo);
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// Now install the observer as the delegate to MF.
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// This will keep all the observers notified about new insertions/deletions.
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RAIIDelegateInstaller DelInstall(MF, &WrapperObserver);
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LegalizerHelper Helper(MF, WrapperObserver, *MIRBuilder.get());
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const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
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LegalizationArtifactCombiner ArtCombiner(*MIRBuilder.get(), MF.getRegInfo(),
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LInfo);
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auto RemoveDeadInstFromLists = [&WrapperObserver](MachineInstr *DeadMI) {
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WrapperObserver.erasingInstr(*DeadMI);
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};
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auto stopLegalizing = [&](MachineInstr &MI) {
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Helper.MIRBuilder.stopObservingChanges();
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reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
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"unable to legalize instruction", MI);
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};
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bool Changed = false;
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SmallVector<MachineInstr *, 128> RetryList;
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do {
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assert(RetryList.empty() && "Expected no instructions in RetryList");
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unsigned NumArtifacts = ArtifactList.size();
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while (!InstList.empty()) {
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MachineInstr &MI = *InstList.pop_back_val();
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assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
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if (isTriviallyDead(MI, MRI)) {
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LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
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MI.eraseFromParentAndMarkDBGValuesForRemoval();
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continue;
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}
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// Do the legalization for this instruction.
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auto Res = Helper.legalizeInstrStep(MI);
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// Error out if we couldn't legalize this instruction. We may want to
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// fall back to DAG ISel instead in the future.
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if (Res == LegalizerHelper::UnableToLegalize) {
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// Move illegal artifacts to RetryList instead of aborting because
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// legalizing InstList may generate artifacts that allow
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// ArtifactCombiner to combine away them.
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if (isArtifact(MI)) {
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RetryList.push_back(&MI);
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continue;
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}
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stopLegalizing(MI);
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return false;
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}
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WorkListObserver.printNewInstrs();
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Changed |= Res == LegalizerHelper::Legalized;
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}
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// Try to combine the instructions in RetryList again if there
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// are new artifacts. If not, stop legalizing.
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if (!RetryList.empty()) {
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if (ArtifactList.size() > NumArtifacts) {
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while (!RetryList.empty())
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ArtifactList.insert(RetryList.pop_back_val());
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} else {
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MachineInstr *MI = *RetryList.begin();
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stopLegalizing(*MI);
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return false;
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}
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}
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while (!ArtifactList.empty()) {
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MachineInstr &MI = *ArtifactList.pop_back_val();
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assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
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if (isTriviallyDead(MI, MRI)) {
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LLVM_DEBUG(dbgs() << MI << "Is dead\n");
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RemoveDeadInstFromLists(&MI);
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MI.eraseFromParentAndMarkDBGValuesForRemoval();
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continue;
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}
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SmallVector<MachineInstr *, 4> DeadInstructions;
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if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions,
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WrapperObserver)) {
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WorkListObserver.printNewInstrs();
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for (auto *DeadMI : DeadInstructions) {
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LLVM_DEBUG(dbgs() << *DeadMI << "Is dead\n");
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RemoveDeadInstFromLists(DeadMI);
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DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
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}
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Changed = true;
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continue;
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}
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// If this was not an artifact (that could be combined away), this might
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// need special handling. Add it to InstList, so when it's processed
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// there, it has to be legal or specially handled.
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else
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InstList.insert(&MI);
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}
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} while (!InstList.empty());
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// For now don't support if new blocks are inserted - we would need to fix the
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// outerloop for that.
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if (MF.size() != NumBlocks) {
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MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
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MF.getFunction().getSubprogram(),
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/*MBB=*/nullptr);
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R << "inserting blocks is not supported yet";
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reportGISelFailure(MF, TPC, MORE, R);
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return false;
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}
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return Changed;
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}
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