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llvm-project/llvm/test/CodeGen/RISCV
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Luís Marques b2aa546b07 [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 
The pass to split atomic and non-atomic RISC-V pseudo-instructions was itself
split into two passes in D79635 / commit rG2cb0644f90b7, with the splitting of
non-atomic instructions being moved to the PreSched2 phase. A comment was
added to D79635 detailing a case where this caused problems, so this commit
moves the non-atomic split pass back to the PreEmitPass2 phase. This allows
the bulk of the changes from D79635 to remain committed, while addressing the
the reported problem (the pass split is now almost NFC). Once the root problem
is fixed we can move the (non-atomic) instruction splitting pass back to
earlier in the pipeline.
 		2020-07-01 16:26:02 +01:00
..
GlobalISel [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
intrinsics [RISCV] Lower llvm.trap and llvm.debugtrap 2019-10-28 09:54:33 +00:00
add-before-shl.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addc-adde-sube-subc.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
addcarry.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
align.ll
…
alloca.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
alu8.ll
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alu16.ll
…
alu32.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
alu64.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
analyze-branch.ll
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arith-with-overflow.ll [TargetLowering] Simplify expansion of S{ADD,SUB}O 2019-09-30 07:58:50 +00:00
atomic-cmpxchg-flag.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
atomic-cmpxchg.ll [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG 2020-04-01 15:51:26 +01:00
atomic-fence.ll
…
atomic-load-store.ll
…
atomic-rmw.ll [MBP] Avoid tail duplication if it can't bring benefit 2019-12-06 09:53:53 -08:00
attributes.ll [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
bare-select.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
blockaddress.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
branch-relaxation.ll [RISCV] Match GNU tools canonical JALR and add aliases 2019-07-16 04:56:43 +00:00
branch.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
byval.ll
…
callee-saved-fpr32s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-fpr64s.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
callee-saved-gprs.ll [RISCV] Remove RA from reserved register to use as callee saved register 2019-10-29 11:32:16 +08:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-ilp32d.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-lp64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-rv32f-ilp32.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
calling-conv-sext-zext.ll
…
calls.ll [RISCV] Lower calls through PLT 2019-06-18 14:29:45 +00:00
codemodel-lowering.ll [RISCV] Temporarily move riscv-expand-pseudo pass to PreEmitPass2 2020-07-01 16:26:02 +01:00
compress-float.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress-inline-asm.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
copysign-casts.ll [LegalizeTypes][RISCV] Soften FCOPYSIGN operand 2019-11-26 15:22:55 +00:00
disable-tail-calls.ll
…
disjoint.ll [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook 2019-11-05 09:39:06 +00:00
div.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-arith.ll [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
double-bitmanip-dagcombines.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-br-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-calling-conv.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-frem.ll
…
double-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
double-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-isnan.ll [RISCV] Add patterns for checking isnan 2020-05-02 15:01:04 +01:00
double-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-previous-failure.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
double-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
double-stack-spill-restore.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
dwarf-eh.ll [RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll 2019-07-17 14:04:48 +00:00
exception-pointer-register.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
fastcc-float.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fastcc-int.ll [RISCV] Support fast calling convention 2019-10-15 02:04:29 +00:00
fixups-diff.ll
…
fixups-relax-diff.ll [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. 2019-07-19 02:03:34 +00:00
float-arith.ll [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
float-bit-preserving-dagcombines.ll [RISCV] Support Bit-Preserving FP in F/D Extensions 2019-06-07 12:20:14 +00:00
float-bitmanip-dagcombines.ll
…
float-br-fcmp.ll [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-frem.ll
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float-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
float-intrinsics.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-isnan.ll [RISCV] Add patterns for checking isnan 2020-05-02 15:01:04 +01:00
float-mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
float-select-fcmp.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
flt-rounds.ll
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fold-addi-loadstore.ll [RISCV][NFC] Add tests for folds of ADDIs into load/stores 2020-06-23 22:59:54 +01:00
fp-imm.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
fp16-promote.ll [RISCV] Add support for half-precision floats 2019-10-25 14:02:02 +01:00
fp128.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
frame-info.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frame.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
frameaddr-returnaddr.ll
…
get-register-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-register-noreserve.ll [RISCV] Implement the TargetLowering::getRegisterByName hook 2019-11-04 11:23:54 +00:00
get-register-reserve.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
get-setcc-result-type.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
hoist-global-addr-base.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
i32-icmp.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
imm-cse.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
imm.ll [RISCV][NFC] Add more constant materialization tests 2020-05-06 16:06:16 +01:00
indirectbr.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
init-array.ll
…
inline-asm-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-clobbers.ll [RISCV] Add support for lowering floating point inlineasm clobbers 2019-07-31 09:07:21 +00:00
inline-asm-d-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-d-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-f-abi-names.ll [RISCV] Allow ABI Names in Inline Assembly Constraints 2019-08-08 14:59:16 +00:00
inline-asm-f-constraint-f.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
inline-asm-i-constraint-i1.ll [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
inline-asm-invalid.ll Emit diagnostic if an inline asm constraint requires an immediate 2019-08-03 05:52:47 +00:00
inline-asm.ll [RISCV] Fix test for inline asm z constraint modifier 2020-01-15 13:50:50 +00:00
interrupt-attr-args-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-callee.ll [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler 2020-02-15 09:14:04 +08:00
interrupt-attr-invalid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
interrupt-attr-ret-error.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
interrupt-attr.ll Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
jumptable.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
large-stack.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
legalize-fneg.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
lit.local.cfg
…
lsr-legaladdimm.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
machineoutliner.mir [RISCV] Enable the machine outliner for RISC-V 2019-12-19 16:41:53 +00:00
mattr-invalid-combination.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mem.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mem64.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
mir-target-flags.ll [RISCV] Fix mir-target-flags.ll 2019-12-09 13:51:08 +00:00
module-target-abi.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
module-target-abi2.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
mul.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
musttail-call.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
nomerge.ll Add NoMerge MIFlag to avoid MIR branch folding 2020-05-29 12:31:06 -07:00
option-nopic.ll [RISCV][AsmParser] Implement .option (no)pic 2020-04-17 12:08:30 +00:00
option-norelax.ll [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` 2020-03-05 18:05:28 -08:00
option-norvc.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
option-pic.ll [RISCV][AsmParser] Implement .option (no)pic 2020-04-17 12:08:30 +00:00
option-relax.ll [llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:` 2020-03-05 18:05:28 -08:00
option-rvc.ll [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
pic-models.ll [RISCV] Add lowering of addressing sequences for PIC 2019-06-11 12:57:47 +00:00
pr40333.ll
…
prefetch.ll
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readcyclecounter.ll [RISCV] Support @llvm.readcyclecounter() Intrinsic 2019-07-05 12:35:21 +00:00
rem.ll
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remat.ll [RISCV][NFC] Fix use of missing attribute groups in tests 2019-12-23 15:39:04 +00:00
reserved-reg-errors.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
reserved-regs.ll [RISCV] Add support for -ffixed-xX flags 2019-10-22 21:25:01 +01:00
rotl-rotr.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv32e.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
rv32i-rv64i-float-double.ll [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall 2019-08-28 23:40:37 +00:00
rv64-large-stack.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
rv64d-double-convert.ll
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rv64f-float-convert.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-complex-float.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64i-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64i-single-softfloat.ll [RISCV64] Emit correct lib call for fp(float/double) to ui/si 2020-06-18 19:34:16 +05:30
rv64i-tricky-shifts.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
rv64i-w-insts-legalization.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
rv64m-exhaustive-w-insts.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
rv64m-w-insts-legalization.ll [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions 2019-08-06 00:24:00 +00:00
saverestore.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
select-cc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
select-const.ll [RISCV] Support Constant Pools in Load/Store Peephole 2020-05-11 19:20:38 +01:00
select-optimize-multiple.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
select-optimize-multiple.mir [MachineVerifier] Verify that a DBG_VALUE has a debug location 2020-05-28 13:53:40 -07:00
select-or.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00
setcc-logic.ll [RISCV] Optimize seteq/setne pattern expansions for better code size 2020-02-11 22:45:15 +08:00
sext-zext-trunc.ll [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
shift-masked-shamt.ll
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shifts.ll Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation. 2019-12-05 14:32:11 +08:00
shrinkwrap.ll [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
split-offsets.ll [RISCV] Fix wrong CFI directives 2019-11-14 18:29:50 +00:00
split-sp-adjust.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
srem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
srem-vector-lkk.ll [TargetLowering] SimplifyDemandedBits - Remove ashr if all our demandedbits already match the sign bit 2020-01-25 17:36:46 +00:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Handle variable sized objects with the stack need to be realigned 2019-11-16 12:39:53 +08:00
stack-realignment.ll [RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore 2019-10-04 02:00:57 +00:00
subtarget-features-std-ext.ll [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
tail-calls.ll [RISCV] Implement mayBeEmittedAsTailCall for tail call optimization 2020-02-18 23:56:42 +08:00
target-abi-invalid.ll
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target-abi-valid.ll Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
thread-pointer.ll [RISCV] Support llvm.thread.pointer 2020-03-27 17:30:12 -07:00
tls-models.ll [RISCV] Don't force Local Exec TLS for non-PIC 2019-12-03 22:04:54 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Switch to the Machine Scheduler 2019-09-17 11:15:35 +00:00
urem-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
urem-vector-lkk.ll [RISCV][NFC] Add nounwind to LKK test functions 2019-11-11 09:51:37 +00:00
vararg.ll [DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) 2020-06-12 13:53:08 -04:00
verify-instr.mir Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
wide-mem.ll
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zext-with-load-is-free.ll [RISCV] Implement Hooks to avoid chaining SELECT 2020-07-01 11:56:31 +01:00