forked from OSchip/llvm-project
118 lines
5.7 KiB
LLVM
118 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -irce -verify-loop-info -verify < %s 2>&1 | FileCheck %s
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; RUN: opt -S -verify-loop-info -passes=irce,verify < %s 2>&1 | FileCheck %s
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define i32 @test_01(i32 %A, i64 %Len, i32 *%array) {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: preheader:
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; CHECK-NEXT: [[TRIPCHECK:%.*]] = icmp sgt i64 [[LEN:%.*]], 2
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; CHECK-NEXT: br i1 [[TRIPCHECK]], label [[LOOP_PREHEADER:%.*]], label [[ZERO:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[A:%.*]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1
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; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[LEN]], i64 0)
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; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[LEN]], [[SMIN]]
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; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP1]])
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; CHECK-NEXT: [[EXIT_MAINLOOP_AT:%.*]] = call i64 @llvm.umax.i64(i64 [[UMIN]], i64 1)
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i64 1, [[EXIT_MAINLOOP_AT]]
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; CHECK-NEXT: br i1 [[TMP3]], label [[LOOP_PREHEADER2:%.*]], label [[MAIN_PSEUDO_EXIT:%.*]]
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; CHECK: loop.preheader2:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], [[LATCH:%.*]] ], [ 1, [[LOOP_PREHEADER2]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i64 [[INDVAR]], [[LEN]]
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; CHECK-NEXT: br i1 true, label [[GUARDED:%.*]], label [[DEOPT_LOOPEXIT3:%.*]]
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; CHECK: guarded:
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; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i32, i32* [[ARRAY:%.*]], i64 [[INDVAR]]
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; CHECK-NEXT: [[RES:%.*]] = load i32, i32* [[ADDR]], align 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[RES]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[ZERO_LOOPEXIT_LOOPEXIT4:%.*]], label [[LATCH]]
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; CHECK: latch:
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; CHECK-NEXT: [[INDVAR_NEXT]] = add nuw nsw i64 [[INDVAR]], 2
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; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], 3
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; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[A]] to i64
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i64 [[INDVAR_NEXT]], [[TMP5]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[INDVAR_NEXT]], [[EXIT_MAINLOOP_AT]]
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; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP6]], true
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; CHECK-NEXT: br i1 [[TMP7]], label [[MAIN_EXIT_SELECTOR:%.*]], label [[LOOP]]
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; CHECK: main.exit.selector:
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; CHECK-NEXT: [[INDVAR_NEXT_LCSSA:%.*]] = phi i64 [ [[INDVAR_NEXT]], [[LATCH]] ]
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; CHECK-NEXT: [[RES2_LCSSA1:%.*]] = phi i32 [ [[RES2]], [[LATCH]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i64 [[INDVAR_NEXT_LCSSA]], [[TMP1]]
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; CHECK-NEXT: br i1 [[TMP8]], label [[MAIN_PSEUDO_EXIT]], label [[LOOPEXIT:%.*]]
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; CHECK: main.pseudo.exit:
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; CHECK-NEXT: [[INDVAR_COPY:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[INDVAR_NEXT_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]
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; CHECK-NEXT: [[INDVAR_END:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[INDVAR_NEXT_LCSSA]], [[MAIN_EXIT_SELECTOR]] ]
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; CHECK-NEXT: br label [[POSTLOOP:%.*]]
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; CHECK: loopexit.loopexit:
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; CHECK-NEXT: [[RES2_LCSSA_PH:%.*]] = phi i32 [ [[RES2_POSTLOOP:%.*]], [[LATCH_POSTLOOP:%.*]] ]
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; CHECK-NEXT: br label [[LOOPEXIT]]
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; CHECK: loopexit:
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; CHECK-NEXT: [[RES2_LCSSA:%.*]] = phi i32 [ [[RES2_LCSSA1]], [[MAIN_EXIT_SELECTOR]] ], [ [[RES2_LCSSA_PH]], [[LOOPEXIT_LOOPEXIT:%.*]] ]
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; CHECK-NEXT: ret i32 [[RES2_LCSSA]]
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; CHECK: zero.loopexit.loopexit:
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; CHECK-NEXT: br label [[ZERO_LOOPEXIT:%.*]]
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; CHECK: zero.loopexit.loopexit4:
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; CHECK-NEXT: br label [[ZERO_LOOPEXIT]]
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; CHECK: zero.loopexit:
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; CHECK-NEXT: br label [[ZERO]]
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; CHECK: zero:
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; CHECK-NEXT: ret i32 0
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; CHECK: deopt.loopexit:
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; CHECK-NEXT: br label [[DEOPT:%.*]]
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; CHECK: deopt.loopexit3:
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; CHECK-NEXT: br label [[DEOPT]]
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; CHECK: deopt:
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; CHECK-NEXT: ret i32 1
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; CHECK: postloop:
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; CHECK-NEXT: br label [[LOOP_POSTLOOP:%.*]]
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; CHECK: loop.postloop:
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; CHECK-NEXT: [[INDVAR_POSTLOOP:%.*]] = phi i64 [ [[INDVAR_NEXT_POSTLOOP:%.*]], [[LATCH_POSTLOOP]] ], [ [[INDVAR_COPY]], [[POSTLOOP]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i64 [[INDVAR_POSTLOOP]], [[LEN]]
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; CHECK-NEXT: br i1 [[TMP9]], label [[GUARDED_POSTLOOP:%.*]], label [[DEOPT_LOOPEXIT:%.*]]
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; CHECK: guarded.postloop:
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; CHECK-NEXT: [[ADDR_POSTLOOP:%.*]] = getelementptr inbounds i32, i32* [[ARRAY]], i64 [[INDVAR_POSTLOOP]]
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; CHECK-NEXT: [[RES_POSTLOOP:%.*]] = load i32, i32* [[ADDR_POSTLOOP]], align 4
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; CHECK-NEXT: [[CMP_POSTLOOP:%.*]] = icmp eq i32 [[RES_POSTLOOP]], 0
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; CHECK-NEXT: br i1 [[CMP_POSTLOOP]], label [[ZERO_LOOPEXIT_LOOPEXIT:%.*]], label [[LATCH_POSTLOOP]]
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; CHECK: latch.postloop:
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; CHECK-NEXT: [[INDVAR_NEXT_POSTLOOP]] = add nuw nsw i64 [[INDVAR_POSTLOOP]], 2
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; CHECK-NEXT: [[RES2_POSTLOOP]] = mul i32 [[RES_POSTLOOP]], 3
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; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[A]] to i64
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; CHECK-NEXT: [[CMP2_POSTLOOP:%.*]] = icmp ugt i64 [[INDVAR_NEXT_POSTLOOP]], [[TMP10]]
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; CHECK-NEXT: br i1 [[CMP2_POSTLOOP]], label [[LOOPEXIT_LOOPEXIT]], label [[LOOP_POSTLOOP]], [[LOOP0:!llvm.loop !.*]], !irce.loop.clone !5
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;
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preheader:
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%tripcheck = icmp sgt i64 %Len, 2
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br i1 %tripcheck, label %loop, label %zero
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loop:
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%indvar = phi i64 [ 1, %preheader ], [ %indvar.next, %latch ]
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%0 = icmp ult i64 %indvar, %Len
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br i1 %0, label %guarded, label %deopt
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guarded:
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%addr = getelementptr inbounds i32, i32* %array, i64 %indvar
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%res = load i32, i32* %addr
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%cmp = icmp eq i32 %res, 0
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br i1 %cmp, label %zero, label %latch
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latch:
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%indvar.next = add nuw nsw i64 %indvar, 2
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%res2 = mul i32 %res, 3
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; NOTE: this is loop invariant value, but not loop invariant instruction!
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%1 = zext i32 %A to i64
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%cmp2 = icmp ugt i64 %indvar.next, %1
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br i1 %cmp2, label %loopexit, label %loop
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loopexit:
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ret i32 %res2
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zero:
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ret i32 0
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deopt:
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ret i32 1
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}
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