forked from OSchip/llvm-project
222 lines
7.9 KiB
LLVM
222 lines
7.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -constraint-elimination -S %s | FileCheck %s
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define i1 @test_add_nuw(i8 %start, i8 %low, i8 %high) {
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; CHECK-LABEL: @test_add_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[ADD_PTR_I:%.*]] = add nuw i8 [[START:%.*]], 3
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; CHECK-NEXT: [[C_1:%.*]] = icmp uge i8 [[ADD_PTR_I]], [[HIGH:%.*]]
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; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: [[UC_3:%.*]] = icmp ugt i8 [[START]], [[HIGH]]
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; CHECK-NEXT: [[START_1_1:%.*]] = add nuw i8 [[START]], 1
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; CHECK-NEXT: [[UC_4:%.*]] = icmp uge i8 [[START_1_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_11:%.*]] = xor i1 [[UC_3]], [[UC_4]]
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; CHECK-NEXT: [[START_3_1:%.*]] = add nuw i8 [[START]], 3
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; CHECK-NEXT: [[T_0:%.*]] = icmp uge i8 [[START_3_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_12:%.*]] = xor i1 [[RES_11]], true
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; CHECK-NEXT: [[UC_5:%.*]] = icmp ugt i8 [[START_3_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_13:%.*]] = xor i1 [[RES_12]], [[UC_5]]
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; CHECK-NEXT: [[SC_8:%.*]] = icmp sge i8 [[START_1_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_14:%.*]] = xor i1 [[RES_13]], [[SC_8]]
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; CHECK-NEXT: [[SC_9:%.*]] = icmp sge i8 [[START_3_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_15:%.*]] = xor i1 [[RES_14]], [[SC_9]]
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; CHECK-NEXT: ret i1 [[RES_15]]
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; CHECK: if.else:
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; CHECK-NEXT: [[F_0:%.*]] = icmp ugt i8 [[START]], [[HIGH]]
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; CHECK-NEXT: [[START_1:%.*]] = add nuw i8 [[START]], 1
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; CHECK-NEXT: [[F_1:%.*]] = icmp uge i8 [[START_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_0:%.*]] = xor i1 false, false
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; CHECK-NEXT: [[SC_1:%.*]] = icmp sgt i8 [[START]], [[HIGH]]
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; CHECK-NEXT: [[RES_1:%.*]] = xor i1 [[RES_0]], [[SC_1]]
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; CHECK-NEXT: [[SC_2:%.*]] = icmp sge i8 [[START_1]], [[HIGH]]
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; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[SC_2]]
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; CHECK-NEXT: [[START_2:%.*]] = add nuw i8 [[START]], 2
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; CHECK-NEXT: [[F_2:%.*]] = icmp uge i8 [[START_2]], [[HIGH]]
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; CHECK-NEXT: [[RES_3:%.*]] = xor i1 [[RES_2]], false
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; CHECK-NEXT: [[SC_3:%.*]] = icmp sge i8 [[START_2]], [[HIGH]]
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; CHECK-NEXT: [[RES_4:%.*]] = xor i1 [[RES_3]], [[SC_3]]
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; CHECK-NEXT: [[SC_4:%.*]] = icmp sle i8 [[START_2]], [[START_1]]
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; CHECK-NEXT: [[RES_5:%.*]] = xor i1 [[RES_4]], [[SC_4]]
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; CHECK-NEXT: [[START_3:%.*]] = add nuw i8 [[START]], 3
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; CHECK-NEXT: [[F_3:%.*]] = icmp uge i8 [[START_3]], [[HIGH]]
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; CHECK-NEXT: [[RES_6:%.*]] = xor i1 [[RES_5]], false
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; CHECK-NEXT: [[SC_5:%.*]] = icmp sge i8 [[START_3]], [[START_1]]
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; CHECK-NEXT: [[RES_7:%.*]] = xor i1 [[RES_6]], [[SC_5]]
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; CHECK-NEXT: [[START_4:%.*]] = add nuw i8 [[START]], 4
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; CHECK-NEXT: [[UC_2:%.*]] = icmp uge i8 [[START_4]], [[HIGH]]
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; CHECK-NEXT: [[RES_8:%.*]] = xor i1 [[RES_7]], [[UC_2]]
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; CHECK-NEXT: [[SC_6:%.*]] = icmp sge i8 [[START_4]], [[START_1]]
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; CHECK-NEXT: [[RES_9:%.*]] = xor i1 [[RES_8]], [[SC_6]]
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; CHECK-NEXT: [[SC_7:%.*]] = icmp sge i8 [[START_4]], [[HIGH]]
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; CHECK-NEXT: [[RES_10:%.*]] = xor i1 [[RES_9]], [[SC_7]]
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; CHECK-NEXT: ret i1 [[RES_10]]
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;
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entry:
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%add.ptr.i = add nuw i8 %start, 3
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%c.1 = icmp uge i8 %add.ptr.i, %high
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br i1 %c.1, label %if.then, label %if.else
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if.then:
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%uc.3 = icmp ugt i8 %start, %high
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%start.1.1 = add nuw i8 %start, 1
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%uc.4 = icmp uge i8 %start.1.1, %high
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%res.11 = xor i1 %uc.3, %uc.4
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%start.3.1 = add nuw i8 %start, 3
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%t.0 = icmp uge i8 %start.3.1, %high
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%res.12 = xor i1 %res.11, %t.0
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%uc.5 = icmp ugt i8 %start.3.1, %high
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%res.13 = xor i1 %res.12, %uc.5
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%sc.8 = icmp sge i8 %start.1.1, %high
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%res.14 = xor i1 %res.13, %sc.8
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%sc.9 = icmp sge i8 %start.3.1, %high
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%res.15 = xor i1 %res.14, %sc.9
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ret i1 %res.15
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if.else:
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%f.0 = icmp ugt i8 %start, %high
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%start.1 = add nuw i8 %start, 1
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%f.1 = icmp uge i8 %start.1, %high
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%res.0 = xor i1 %f.0, %f.1
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%sc.1 = icmp sgt i8 %start, %high
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%res.1 = xor i1 %res.0, %sc.1
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%sc.2 = icmp sge i8 %start.1, %high
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%res.2 = xor i1 %res.1, %sc.2
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%start.2 = add nuw i8 %start, 2
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%f.2 = icmp uge i8 %start.2, %high
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%res.3 = xor i1 %res.2, %f.2
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%sc.3 = icmp sge i8 %start.2, %high
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%res.4 = xor i1 %res.3, %sc.3
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%sc.4 = icmp sle i8 %start.2, %start.1
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%res.5 = xor i1 %res.4, %sc.4
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%start.3 = add nuw i8 %start, 3
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%f.3 = icmp uge i8 %start.3, %high
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%res.6 = xor i1 %res.5, %f.3
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%sc.5 = icmp sge i8 %start.3, %start.1
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%res.7 = xor i1 %res.6, %sc.5
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%start.4 = add nuw i8 %start, 4
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%uc.2 = icmp uge i8 %start.4, %high
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%res.8 = xor i1 %res.7, %uc.2
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%sc.6 = icmp sge i8 %start.4, %start.1
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%res.9 = xor i1 %res.8, %sc.6
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%sc.7 = icmp sge i8 %start.4, %high
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%res.10 = xor i1 %res.9, %sc.7
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ret i1 %res.10
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}
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define i1 @test_and_ule_sge(i32 %x, i32 %y, i32 %z, i32 %a) {
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; CHECK-LABEL: @test_and_ule_sge(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C_1:%.*]] = icmp ule i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[C_2:%.*]] = icmp sle i32 [[Y]], [[Z:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i1 [[C_1]], [[C_2]]
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; CHECK-NEXT: br i1 [[AND]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[UC_1:%.*]] = icmp ule i32 [[X]], [[Z]]
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; CHECK-NEXT: [[UC_2:%.*]] = icmp ule i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RES_1:%.*]] = xor i1 [[UC_1]], true
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; CHECK-NEXT: [[UC_3:%.*]] = icmp ule i32 [[Y]], [[Z]]
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; CHECK-NEXT: [[RES_2:%.*]] = xor i1 [[RES_1]], [[UC_3]]
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; CHECK-NEXT: [[UC_4:%.*]] = icmp ule i32 [[X]], [[A:%.*]]
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; CHECK-NEXT: [[RES_4:%.*]] = xor i1 [[RES_2]], [[UC_4]]
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; CHECK-NEXT: [[SC_1:%.*]] = icmp sle i32 [[X]], [[Z]]
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; CHECK-NEXT: [[RES_5:%.*]] = xor i1 [[RES_4]], [[SC_1]]
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; CHECK-NEXT: [[SC_2:%.*]] = icmp sle i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RES_6:%.*]] = xor i1 [[RES_5]], [[SC_2]]
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; CHECK-NEXT: [[SC_3:%.*]] = icmp sle i32 [[Y]], [[Z]]
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; CHECK-NEXT: [[RES_7:%.*]] = xor i1 [[RES_6]], [[SC_3]]
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; CHECK-NEXT: [[SC_4:%.*]] = icmp sle i32 [[X]], [[A]]
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; CHECK-NEXT: [[RES_8:%.*]] = xor i1 [[RES_7]], [[SC_4]]
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; CHECK-NEXT: ret i1 [[RES_8]]
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; CHECK: else:
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; CHECK-NEXT: [[UC_5:%.*]] = icmp ule i32 [[X]], [[Z]]
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; CHECK-NEXT: [[UC_6:%.*]] = icmp ule i32 [[X]], [[A]]
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; CHECK-NEXT: [[RES_9:%.*]] = xor i1 [[UC_5]], [[UC_6]]
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; CHECK-NEXT: [[UC_7:%.*]] = icmp ule i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RES_10:%.*]] = xor i1 [[RES_9]], [[UC_7]]
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; CHECK-NEXT: [[UC_8:%.*]] = icmp ule i32 [[Y]], [[Z]]
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; CHECK-NEXT: [[RES_11:%.*]] = xor i1 [[RES_10]], [[UC_8]]
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; CHECK-NEXT: [[SC_5:%.*]] = icmp sle i32 [[X]], [[Z]]
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; CHECK-NEXT: [[RES_12:%.*]] = xor i1 [[RES_11]], [[SC_5]]
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; CHECK-NEXT: [[SC_6:%.*]] = icmp sle i32 [[X]], [[A]]
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; CHECK-NEXT: [[RES_13:%.*]] = xor i1 [[RES_12]], [[SC_6]]
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; CHECK-NEXT: [[SC_7:%.*]] = icmp sle i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RES_14:%.*]] = xor i1 [[RES_13]], [[SC_7]]
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; CHECK-NEXT: [[SC_8:%.*]] = icmp sle i32 [[Y]], [[Z]]
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; CHECK-NEXT: [[RES_15:%.*]] = xor i1 [[RES_14]], [[SC_8]]
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; CHECK-NEXT: ret i1 [[RES_15]]
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;
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entry:
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%c.1 = icmp ule i32 %x, %y
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%c.2 = icmp sle i32 %y, %z
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%and = and i1 %c.1, %c.2
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br i1 %and, label %then, label %else
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then:
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%uc.1 = icmp ule i32 %x, %z
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%uc.2 = icmp ule i32 %x, %y
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%res.1 = xor i1 %uc.1, %uc.2
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%uc.3 = icmp ule i32 %y, %z
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%res.2 = xor i1 %res.1, %uc.3
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%uc.4 = icmp ule i32 %x, %a
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%res.4 = xor i1 %res.2, %uc.4
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%sc.1 = icmp sle i32 %x, %z
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%res.5 = xor i1 %res.4, %sc.1
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%sc.2 = icmp sle i32 %x, %y
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%res.6 = xor i1 %res.5, %sc.2
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%sc.3 = icmp sle i32 %y, %z
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%res.7 = xor i1 %res.6, %sc.3
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%sc.4 = icmp sle i32 %x, %a
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%res.8 = xor i1 %res.7, %sc.4
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ret i1 %res.8
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else:
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%uc.5 = icmp ule i32 %x, %z
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%uc.6 = icmp ule i32 %x, %a
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%res.9 = xor i1 %uc.5, %uc.6
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%uc.7 = icmp ule i32 %x, %y
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%res.10 = xor i1 %res.9, %uc.7
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%uc.8 = icmp ule i32 %y, %z
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%res.11 = xor i1 %res.10, %uc.8
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%sc.5 = icmp sle i32 %x, %z
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%res.12 = xor i1 %res.11, %sc.5
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%sc.6 = icmp sle i32 %x, %a
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%res.13 = xor i1 %res.12, %sc.6
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%sc.7 = icmp sle i32 %x, %y
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%res.14 = xor i1 %res.13, %sc.7
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%sc.8 = icmp sle i32 %y, %z
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%res.15 = xor i1 %res.14, %sc.8
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ret i1 %res.15
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}
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