forked from OSchip/llvm-project
334 lines
14 KiB
LLVM
334 lines
14 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; Check that we properly realign the stack. While 4-byte access is all
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; that is ever needed, some transformations rely on the known bits from the alignment of the pointer (e.g.
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; 128 byte object
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; 4 byte emergency stack slot
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; = 144 bytes with padding between them
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; GCN-LABEL: {{^}}needs_align16_default_stack_align:
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; GCN-DAG: v_lshlrev_b32_e32 [[SCALED_IDX:v[0-9]+]], 4, v0
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; GCN-DAG: v_lshrrev_b32_e64 [[FRAMEDIFF:v[0-9]+]], 6, s32
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; GCN: v_add_u32_e32 [[FI:v[0-9]+]], vcc, [[FRAMEDIFF]], [[SCALED_IDX]]
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; GCN-NOT: s32
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN-NOT: s32
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; GCN: ; ScratchSize: 144
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define void @needs_align16_default_stack_align(i32 %idx) #0 {
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%alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
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%gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
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store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 16
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ret void
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}
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; GCN-LABEL: {{^}}needs_align16_stack_align4:
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; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0x3c0{{$}}
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; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xfffffc00
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
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; GCN: s_add_u32 s32, s32, 0x2800{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: s_sub_u32 s32, s32, 0x2800
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; GCN: ; ScratchSize: 160
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define void @needs_align16_stack_align4(i32 %idx) #2 {
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%alloca.align16 = alloca [8 x <4 x i32>], align 16, addrspace(5)
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%gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
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store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 16
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ret void
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}
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; GCN-LABEL: {{^}}needs_align32:
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; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0x7c0{{$}}
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; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xfffff800
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: v_or_b32_e32 v{{[0-9]+}}, 12
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; GCN: s_add_u32 s32, s32, 0x3000{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: s_sub_u32 s32, s32, 0x3000
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; GCN: ; ScratchSize: 192
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define void @needs_align32(i32 %idx) #0 {
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%alloca.align16 = alloca [8 x <4 x i32>], align 32, addrspace(5)
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%gep0 = getelementptr inbounds [8 x <4 x i32>], [8 x <4 x i32>] addrspace(5)* %alloca.align16, i32 0, i32 %idx
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store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep0, align 32
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ret void
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}
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; GCN-LABEL: {{^}}force_realign4:
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; GCN: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xc0{{$}}
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; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffffff00
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; GCN: s_add_u32 s32, s32, 0xd00{{$}}
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; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen
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; GCN: s_sub_u32 s32, s32, 0xd00
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; GCN: ; ScratchSize: 52
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define void @force_realign4(i32 %idx) #1 {
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%alloca.align16 = alloca [8 x i32], align 4, addrspace(5)
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%gep0 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca.align16, i32 0, i32 %idx
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store volatile i32 3, i32 addrspace(5)* %gep0, align 4
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_align16_from_8:
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; GCN: s_movk_i32 s32, 0x400{{$}}
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; GCN-NOT: s32
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_align16_from_8() #0 {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 2, i32 addrspace(5)* %alloca
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call void @needs_align16_default_stack_align(i32 1)
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ret void
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}
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; The call sequence should keep the stack on call aligned to 4
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; GCN-LABEL: {{^}}kernel_call_align16_from_5:
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; GCN: s_movk_i32 s32, 0x400
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_align16_from_5() {
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%alloca0 = alloca i8, align 1, addrspace(5)
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store volatile i8 2, i8 addrspace(5)* %alloca0
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call void @needs_align16_default_stack_align(i32 1)
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_align4_from_5:
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; GCN: s_movk_i32 s32, 0x400
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_align4_from_5() {
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%alloca0 = alloca i8, align 1, addrspace(5)
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store volatile i8 2, i8 addrspace(5)* %alloca0
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call void @needs_align16_stack_align4(i32 1)
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ret void
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}
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; GCN-LABEL: {{^}}default_realign_align128:
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; GCN: s_mov_b32 [[FP_COPY:s[0-9]+]], s33
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; GCN-NEXT: s_add_u32 s33, s32, 0x1fc0
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; GCN-NEXT: s_and_b32 s33, s33, 0xffffe000
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; GCN-NEXT: s_add_u32 s32, s32, 0x4000
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; GCN-NOT: s33
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; GCN: buffer_store_dword v0, off, s[0:3], s33{{$}}
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; GCN: s_sub_u32 s32, s32, 0x4000
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; GCN: s_mov_b32 s33, [[FP_COPY]]
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define void @default_realign_align128(i32 %idx) #0 {
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%alloca.align = alloca i32, align 128, addrspace(5)
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store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
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ret void
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}
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; GCN-LABEL: {{^}}disable_realign_align128:
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; GCN-NOT: s32
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; GCN: buffer_store_dword v0, off, s[0:3], s32{{$}}
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; GCN-NOT: s32
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define void @disable_realign_align128(i32 %idx) #3 {
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%alloca.align = alloca i32, align 128, addrspace(5)
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store volatile i32 9, i32 addrspace(5)* %alloca.align, align 128
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ret void
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}
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declare void @extern_func(<32 x i32>, i32) #0
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define void @func_call_align1024_bp_gets_vgpr_spill(<32 x i32> %a, i32 %b) #0 {
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; The test forces the stack to be realigned to a new boundary
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; since there is a local object with an alignment of 1024.
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; Should use BP to access the incoming stack arguments.
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; The BP value is saved/restored with a VGPR spill.
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; GCN-LABEL: func_call_align1024_bp_gets_vgpr_spill:
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; GCN: buffer_store_dword [[VGPR_REG:v[0-9]+]], off, s[0:3], s32 offset:1028 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_writelane_b32 [[VGPR_REG]], s33, 2
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; GCN-DAG: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xffc0
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; GCN-DAG: v_writelane_b32 [[VGPR_REG]], s34, 3
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; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffff0000
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; GCN: s_mov_b32 s34, s32
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; GCN: v_mov_b32_e32 v32, 0
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; GCN: buffer_store_dword v32, off, s[0:3], s33 offset:1024
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34
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; GCN-DAG: s_add_u32 s32, s32, 0x30000
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN: s_sub_u32 s32, s32, 0x30000
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; GCN-NEXT: v_readlane_b32 s33, [[VGPR_REG]], 2
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; GCN-NEXT: v_readlane_b32 s34, [[VGPR_REG]], 3
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; GCN-NEXT: s_or_saveexec_b64 s[6:7], -1
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; GCN-NEXT: buffer_load_dword [[VGPR_REG]], off, s[0:3], s32 offset:1028 ; 4-byte Folded Reload
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; GCN-NEXT: s_mov_b64 exec, s[6:7]
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%temp = alloca i32, align 1024, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %temp, align 1024
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call void @extern_func(<32 x i32> %a, i32 %b)
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ret void
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}
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%struct.Data = type { [9 x i32] }
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define i32 @needs_align1024_stack_args_used_inside_loop(%struct.Data addrspace(5)* nocapture readonly byval(%struct.Data) align 8 %arg) local_unnamed_addr #4 {
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; The local object allocation needed an alignment of 1024.
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; Since the function argument is accessed in a loop with an
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; index variable, the base pointer first get loaded into a VGPR
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; and that value should be further referenced to load the incoming values.
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; The BP value will get saved/restored in an SGPR at the prolgoue/epilogue.
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; GCN-LABEL: needs_align1024_stack_args_used_inside_loop:
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; GCN: s_mov_b32 [[FP_COPY:s[0-9]+]], s33
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; GCN-NEXT: s_add_u32 s33, s32, 0xffc0
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; GCN-NEXT: s_mov_b32 [[BP_COPY:s[0-9]+]], s34
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: s_and_b32 s33, s33, 0xffff0000
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; GCN-NEXT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NEXT: v_lshrrev_b32_e64 [[VGPR_REG:v[0-9]+]], 6, s34
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; GCN: s_add_u32 s32, s32, 0x30000
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:1024
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; GCN: buffer_load_dword v{{[0-9]+}}, [[VGPR_REG]], s[0:3], 0 offen
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; GCN: v_add_u32_e32 [[VGPR_REG]], vcc, 4, [[VGPR_REG]]
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; GCN: s_sub_u32 s32, s32, 0x30000
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; GCN-NEXT: s_mov_b32 s33, [[FP_COPY]]
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; GCN-NEXT: s_mov_b32 s34, [[BP_COPY]]
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; GCN-NEXT: s_setpc_b64 s[30:31]
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begin:
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%local_var = alloca i32, align 1024, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %local_var, align 1024
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br label %loop_body
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loop_end: ; preds = %loop_body
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%idx_next = add nuw nsw i32 %lp_idx, 1
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%lp_exit_cond = icmp eq i32 %idx_next, 9
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br i1 %lp_exit_cond, label %exit, label %loop_body
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loop_body: ; preds = %loop_end, %begin
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%lp_idx = phi i32 [ 0, %begin ], [ %idx_next, %loop_end ]
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%ptr = getelementptr inbounds %struct.Data, %struct.Data addrspace(5)* %arg, i32 0, i32 0, i32 %lp_idx
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%val = load i32, i32 addrspace(5)* %ptr, align 8
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%lp_cond = icmp eq i32 %val, %lp_idx
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br i1 %lp_cond, label %loop_end, label %exit
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exit: ; preds = %loop_end, %loop_body
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%out = phi i32 [ 0, %loop_body ], [ 1, %loop_end ]
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ret i32 %out
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}
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define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 {
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; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy:
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; GCN: ; %bb.0:
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; GCN: v_writelane_b32 [[VGPR_REG:v[0-9]+]], s34, 0
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34
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; GCN: v_readlane_b32 s34, [[VGPR_REG:v[0-9]+]], 0
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:128
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: ;;#ASMEND
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; GCN: s_setpc_b64 s[30:31]
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%local_val = alloca i32, align 128, addrspace(5)
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store volatile i32 %b, i32 addrspace(5)* %local_val, align 128
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; Use all clobberable registers, so BP has to spill to a VGPR.
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call void asm sideeffect "",
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"~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
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,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
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,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
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,~{vcc_hi}"() #0
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ret void
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}
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define void @no_free_regs_spill_bp_to_memory(<32 x i32> %a, i32 %b) #5 {
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; If there are no free SGPRs or VGPRs available we must spill the BP to memory.
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; GCN-LABEL: no_free_regs_spill_bp_to_mem
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; GCN: s_or_saveexec_b64 s[4:5], -1
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; GCN: v_mov_b32_e32 v0, s33
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; GCN: buffer_store_dword v0, off, s[0:3], s32
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; GCN: v_mov_b32_e32 v0, s34
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; GCN-DAG: buffer_store_dword v0, off, s[0:3], s32
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%local_val = alloca i32, align 128, addrspace(5)
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store volatile i32 %b, i32 addrspace(5)* %local_val, align 128
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call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
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"~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
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,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
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,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
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,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
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,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59}
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,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65},~{s66},~{s67},~{s68},~{s69}
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,~{s70},~{s71},~{s72},~{s73},~{s74},~{s75},~{s76},~{s77},~{s78},~{s79}
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,~{s80},~{s81},~{s82},~{s83},~{s84},~{s85},~{s86},~{s87},~{s88},~{s89}
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,~{s90},~{s91},~{s92},~{s93},~{s94},~{s95},~{s96},~{s97},~{s98},~{s99}
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,~{s100},~{s101},~{s102},~{s39},~{vcc}"() #0
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call void asm sideeffect "; clobber all VGPRs",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
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,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38}" () #0
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ret void
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}
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define void @spill_bp_to_memory_scratch_reg_needed_mubuf_offset(<32 x i32> %a, i32 %b, [4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #5 {
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; If the size of the offset exceeds the MUBUF offset field we need another
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; scratch VGPR to hold the offset.
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; GCN-LABEL: spill_bp_to_memory_scratch_reg_needed_mubuf_offset
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; GCN: s_or_saveexec_b64 s[4:5], -1
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; GCN-NEXT: s_add_u32 s6, s32, 0x42100
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; GCN-NEXT: buffer_store_dword v39, off, s[0:3], s6 ; 4-byte Folded Spill
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; GCN-NEXT: s_mov_b64 exec, s[4:5]
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; GCN-NEXT: v_mov_b32_e32 v0, s33
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; GCN-NOT: v_mov_b32_e32 v0, 0x1088
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; GCN-NEXT: s_add_u32 s6, s32, 0x42200
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
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; GCN-NEXT: v_mov_b32_e32 v0, s34
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; GCN-NOT: v_mov_b32_e32 v0, 0x108c
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; GCN-NEXT: s_add_u32 s6, s32, 0x42300
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; GCN-NEXT: s_mov_b32 s34, s32
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
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%local_val = alloca i32, align 128, addrspace(5)
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store volatile i32 %b, i32 addrspace(5)* %local_val, align 128
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call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
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"~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
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,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
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,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
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,~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
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,~{s50},~{s51},~{s52},~{s53},~{s54},~{s55},~{s56},~{s57},~{s58},~{s59}
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,~{s60},~{s61},~{s62},~{s63},~{s64},~{s65},~{s66},~{s67},~{s68},~{s69}
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,~{s70},~{s71},~{s72},~{s73},~{s74},~{s75},~{s76},~{s77},~{s78},~{s79}
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,~{s80},~{s81},~{s82},~{s83},~{s84},~{s85},~{s86},~{s87},~{s88},~{s89}
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,~{s90},~{s91},~{s92},~{s93},~{s94},~{s95},~{s96},~{s97},~{s98},~{s99}
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,~{s100},~{s101},~{s102},~{s39},~{vcc}"() #0
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call void asm sideeffect "; clobber all VGPRs",
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"~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9}
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,~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}
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,~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}
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,~{v30},~{v31},~{v32},~{v33},~{v34},~{v35},~{v36},~{v37},~{v38}"() #0
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ret void
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}
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attributes #0 = { noinline nounwind }
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attributes #1 = { noinline nounwind "stackrealign" }
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attributes #2 = { noinline nounwind alignstack=4 }
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attributes #3 = { noinline nounwind "no-realign-stack" }
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attributes #4 = { noinline nounwind "frame-pointer"="all"}
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attributes #5 = { noinline nounwind "amdgpu-waves-per-eu"="6,6" }
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