forked from OSchip/llvm-project
36 lines
1.4 KiB
LLVM
36 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
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; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
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; GCN-LABEL: {{^}}test:
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; GCN: enable_sgpr_dispatch_ptr = 1
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; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
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define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
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%dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
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%header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
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%value = load i32, i32 addrspace(4)* %header_ptr
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test2
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; GCN: enable_sgpr_dispatch_ptr = 1
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; GCN: s_load_dword s[[REG:[0-9]+]], s[4:5], 0x1
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; GCN: s_lshr_b32 s{{[0-9]+}}, s[[REG]], 16
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; GCN-NOT: load_ushort
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; GCN: s_endpgm
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define amdgpu_kernel void @test2(i32 addrspace(1)* %out) {
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%dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
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%d1 = getelementptr inbounds i8, i8 addrspace(4)* %dispatch_ptr, i64 6
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%h1 = bitcast i8 addrspace(4)* %d1 to i16 addrspace(4)*
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%v1 = load i16, i16 addrspace(4)* %h1
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%e1 = zext i16 %v1 to i32
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store i32 %e1, i32 addrspace(1)* %out
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ret void
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}
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declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
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attributes #0 = { readnone }
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