forked from OSchip/llvm-project
34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The first load produces address in a VGPR which is used in address calculation
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; of the second load (one inside the loop). The value is uniform and the inner
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; load correctly selected to use SADDR form, however the address is promoted to
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; vector registers because it all starts with a VGPR produced by the entry block
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; load.
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;
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; Check that we are changing SADDR form of a load to VADDR and do not have to use
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; readfirstlane instructions to move address from VGPRs into SGPRs.
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; GCN-LABEL: {{^}}test_move_load_address_to_vgpr:
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; GCN: BB{{[0-9]+}}_1:
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; GCN-NOT: v_readfirstlane_b32
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; GCN: global_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}], off glc
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define amdgpu_kernel void @test_move_load_address_to_vgpr(i32 addrspace(1)* nocapture %arg) {
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bb:
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%i1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 0
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%i2 = load volatile i32, i32 addrspace(1)* %i1, align 4
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]
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%i4 = zext i32 %i to i64
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%i5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %i4
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%i6 = load volatile i32, i32 addrspace(1)* %i5, align 4
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%i8 = add nuw nsw i32 %i, 1
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%i9 = icmp eq i32 %i8, 256
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br i1 %i9, label %bb2, label %bb3
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}
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