forked from OSchip/llvm-project
163 lines
8.1 KiB
LLVM
163 lines
8.1 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs -debug-only=machine-scheduler < %s 2> %t | FileCheck --enable-var-scope --check-prefixes=CHECK,GCN %s
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; RUN: FileCheck --enable-var-scope --check-prefixes=CHECK,DBG %s < %t
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; REQUIRES: asserts
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; FIXME: Verifier error with xnack enabled.
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; CHECK-LABEL: {{^}}cluster_load_cluster_store:
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define amdgpu_kernel void @cluster_load_cluster_store(i32* noalias %lb, i32* noalias %sb) {
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bb:
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Cluster ld/st SU(1) - SU(2)
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; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
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; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
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; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
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; GCN: flat_load_dword [[LD1:v[0-9]+]], v[{{[0-9:]+}}]
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; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8
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; GCN-NEXT: flat_load_dword [[LD3:v[0-9]+]], v[{{[0-9:]+}}] offset:16
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; GCN-NEXT: flat_load_dword [[LD4:v[0-9]+]], v[{{[0-9:]+}}] offset:24
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%la0 = getelementptr inbounds i32, i32* %lb, i32 0
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%ld0 = load i32, i32* %la0
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%la1 = getelementptr inbounds i32, i32* %lb, i32 2
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%ld1 = load i32, i32* %la1
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%la2 = getelementptr inbounds i32, i32* %lb, i32 4
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%ld2 = load i32, i32* %la2
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%la3 = getelementptr inbounds i32, i32* %lb, i32 6
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%ld3 = load i32, i32* %la3
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; DBG-NOT: Cluster ld/st
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[LD1]]
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD2]] offset:8
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD3]] offset:16
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD4]] offset:24
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%sa0 = getelementptr inbounds i32, i32* %sb, i32 0
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store i32 %ld0, i32* %sa0
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%sa1 = getelementptr inbounds i32, i32* %sb, i32 2
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store i32 %ld1, i32* %sa1
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%sa2 = getelementptr inbounds i32, i32* %sb, i32 4
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store i32 %ld2, i32* %sa2
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%sa3 = getelementptr inbounds i32, i32* %sb, i32 6
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store i32 %ld3, i32* %sa3
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ret void
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}
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; CHECK-LABEL: {{^}}cluster_load_valu_cluster_store:
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define amdgpu_kernel void @cluster_load_valu_cluster_store(i32* noalias %lb, i32* noalias %sb) {
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bb:
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 8
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 4
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; DBG: Cluster ld/st SU(1) - SU(2)
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; DBG: Cluster ld/st SU([[L1:[0-9]+]]) - SU([[L2:[0-9]+]])
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; DBG: Cluster ld/st SU([[L2]]) - SU([[L3:[0-9]+]])
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; DBG: Cluster ld/st SU([[L3]]) - SU([[L4:[0-9]+]])
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; GCN: flat_load_dword [[LD1:v[0-9]+]], v[{{[0-9:]+}}]
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; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8
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; GCN-NEXT: flat_load_dword [[LD3:v[0-9]+]], v[{{[0-9:]+}}] offset:16
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; GCN-NEXT: flat_load_dword [[LD4:v[0-9]+]], v[{{[0-9:]+}}] offset:24
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%la0 = getelementptr inbounds i32, i32* %lb, i32 0
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%ld0 = load i32, i32* %la0
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%la1 = getelementptr inbounds i32, i32* %lb, i32 2
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%ld1 = load i32, i32* %la1
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%la2 = getelementptr inbounds i32, i32* %lb, i32 4
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%ld2 = load i32, i32* %la2
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%la3 = getelementptr inbounds i32, i32* %lb, i32 6
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%ld3 = load i32, i32* %la3
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; DBG-NOT: Cluster ld/st
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; GCN: flat_store_dword v[{{[0-9:]+}}], [[LD1]]
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; GCN: v_add_u32_e32 [[ST2:v[0-9]+]], 1, [[LD2]]
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD3]] offset:16
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[ST2]] offset:8
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; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD4]] offset:24
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%sa0 = getelementptr inbounds i32, i32* %sb, i32 0
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store i32 %ld0, i32* %sa0
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%sa1 = getelementptr inbounds i32, i32* %sb, i32 2
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%add = add i32 %ld1, 1
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store i32 %add, i32* %sa1
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%sa2 = getelementptr inbounds i32, i32* %sb, i32 4
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store i32 %ld2, i32* %sa2
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%sa3 = getelementptr inbounds i32, i32* %sb, i32 6
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store i32 %ld3, i32* %sa3
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ret void
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}
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; Cluster loads from the same texture with different coordinates
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; CHECK-LABEL: {{^}}cluster_image_load:
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
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; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_LOAD
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; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_LOAD
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; GCN: image_load v
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; GCN-NEXT: image_load v
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define amdgpu_ps void @cluster_image_load(<8 x i32> inreg %src, <8 x i32> inreg %dst, i32 %x, i32 %y) {
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entry:
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%x1 = add i32 %x, 1
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%y1 = add i32 %y, 1
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%val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x1, i32 %y1, i32 0, <8 x i32> %src, i32 0, i32 0)
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%x2 = add i32 %x, 2
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%y2 = add i32 %y, 2
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%val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x2, i32 %y2, i32 0, <8 x i32> %src, i32 0, i32 0)
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%val = fadd fast <4 x float> %val1, %val2
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call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
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ret void
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}
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; Don't cluster loads from different textures
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; CHECK-LABEL: {{^}}no_cluster_image_load:
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG-NOT: {{^}}Cluster ld/st
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define amdgpu_ps void @no_cluster_image_load(<8 x i32> inreg %src1, <8 x i32> inreg %src2, <8 x i32> inreg %dst, i32 %x, i32 %y) {
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entry:
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%val1 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src1, i32 0, i32 0)
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%val2 = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %x, i32 %y, i32 0, <8 x i32> %src2, i32 0, i32 0)
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%val = fadd fast <4 x float> %val1, %val2
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call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
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ret void
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}
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; Cluster loads from the same texture and sampler with different coordinates
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; CHECK-LABEL: {{^}}cluster_image_sample:
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG: Num BaseOps: {{[1-9]+}}, Offset: {{[0-9]+}}, OffsetIsScalable: {{[01]}}, Width: 16
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; DBG: {{^}}Cluster ld/st [[SU1:SU\([0-9]+\)]] - [[SU2:SU\([0-9]+\)]]
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; DBG: {{^}}[[SU1]]: {{.*}} IMAGE_SAMPLE
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; DBG: {{^}}[[SU2]]: {{.*}} IMAGE_SAMPLE
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; GCN: image_sample_d
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; GCN-NEXT: image_sample_d
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define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inreg %smp, <8 x i32> inreg %dst, i32 %x, i32 %y) {
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entry:
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%s = sitofp i32 %x to float
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%t = sitofp i32 %y to float
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%s1 = fadd float %s, 1.0
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%t1 = fadd float %t, 1.0
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%val1 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s1, float %t1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
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%s2 = fadd float %s, 2.0
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%t2 = fadd float %t, 2.0
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%val2 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32 15, float %s2, float %t2, float 1.0, float 1.0, float 1.0, float 1.0, <8 x i32> %src, <4 x i32> %smp, i1 false, i32 0, i32 0)
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%val = fadd fast <4 x float> %val1, %val2
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call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %val, i32 15, i32 %x, i32 %y, <8 x i32> %dst, i32 0, i32 0)
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ret void
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}
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declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
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declare void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float>, i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg)
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