forked from OSchip/llvm-project
3641b10f3d
Vector load/store instructions support an optional alignment field that the compiler can use to provide known alignment info to the hardware. If the field is used (and the information is correct), the hardware may be able (on some models) to perform faster memory accesses than otherwise. This patch adds support for alignment hints in the assembler and disassembler, and fills in known alignment during codegen. llvm-svn: 363806 |
||
|---|---|---|
| .. | ||
| asm-match.s | ||
| directive-insn.s | ||
| fixups-zEC12.s | ||
| fixups.s | ||
| insn-bad-z13.s | ||
| insn-bad-z14.s | ||
| insn-bad-z196.s | ||
| insn-bad-zEC12.s | ||
| insn-bad.s | ||
| insn-good-z13.s | ||
| insn-good-z14.s | ||
| insn-good-z196.s | ||
| insn-good-zEC12.s | ||
| insn-good.s | ||
| invalid-instructions-spellcheck.s | ||
| lit.local.cfg | ||
| regs-bad.s | ||
| regs-good.s | ||
| tokens.s | ||
| word.s | ||