forked from OSchip/llvm-project
316 lines
11 KiB
LLVM
316 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse4.1 | FileCheck %s
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; This test works just like the non-upgrade one except that it only checks
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; forms which require auto-upgrading.
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define <2 x double> @test_x86_sse41_blendpd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK-LABEL: test_x86_sse41_blendpd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: blendpd {{.*#+}} xmm0 = xmm0[0],xmm1[1]
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; CHECK-NEXT: retl
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%res = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %a0, <2 x double> %a1, i32 6) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i32) nounwind readnone
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define <4 x float> @test_x86_sse41_blendps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: test_x86_sse41_blendps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) {
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; CHECK-LABEL: test_x86_sse41_dppd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: dppd $7, %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse41.dppd(<2 x double>, <2 x double>, i32) nounwind readnone
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define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: test_x86_sse41_dpps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: dpps $7, %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i32 7) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) {
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; CHECK-LABEL: test_x86_sse41_insertps:
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; CHECK: ## BB#0:
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; CHECK-NEXT: insertps {{.*#+}} xmm0 = zero,xmm1[0],xmm0[2,3]
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; CHECK-NEXT: retl
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%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i32 17) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <2 x i64> @test_x86_sse41_movntdqa(<2 x i64>* %a0) {
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; CHECK-LABEL: test_x86_sse41_movntdqa:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movntdqa (%eax), %xmm0
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; CHECK-NEXT: retl
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%arg0 = bitcast <2 x i64>* %a0 to i8*
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%res = call <2 x i64> @llvm.x86.sse41.movntdqa(i8* %arg0)
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.movntdqa(i8*) nounwind readnone
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define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: test_x86_sse41_mpsadbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: mpsadbw $7, %xmm1, %xmm0
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; CHECK-NEXT: retl
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%res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i32 7) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i32) nounwind readnone
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define <8 x i16> @test_x86_sse41_pblendw(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: test_x86_sse41_pblendw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3,4,5,6,7]
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; CHECK-NEXT: retl
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%res = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %a0, <8 x i16> %a1, i32 7) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i32) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmovsxbd(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxbd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxbd %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovsxbq(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxbq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxbq %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
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define <8 x i16> @test_x86_sse41_pmovsxbw(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxbw %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovsxdq(<4 x i32> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxdq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxdq %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmovsxwd(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxwd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxwd %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovsxwq(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovsxwq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovsxwq %xmm0, %xmm0
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmovzxbd(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxbd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8> %a0) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmovzxbd(<16 x i8>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovzxbq(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxbq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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define <8 x i16> @test_x86_sse41_pmovzxbw(<16 x i8> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxbw:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: retl
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%res = call <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8> %a0) ; <<8 x i16>> [#uses=1]
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pmovzxbw(<16 x i8>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovzxdq(<4 x i32> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxdq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxdq(<4 x i32>) nounwind readnone
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define <4 x i32> @test_x86_sse41_pmovzxwd(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxwd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; CHECK-NEXT: retl
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%res = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %a0) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
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define <2 x i64> @test_x86_sse41_pmovzxwq(<8 x i16> %a0) {
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; CHECK-LABEL: test_x86_sse41_pmovzxwq:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
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; CHECK-NEXT: retl
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%res = call <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16> %a0) ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %res
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}
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declare <2 x i64> @llvm.x86.sse41.pmovzxwq(<8 x i16>) nounwind readnone
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define <16 x i8> @max_epi8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: max_epi8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxsb %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <16 x i8> @min_epi8(<16 x i8> %a0, <16 x i8> %a1) {
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; CHECK-LABEL: min_epi8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminsb %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8>, <16 x i8>) nounwind readnone
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define <8 x i16> @max_epu16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: max_epu16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxuw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <8 x i16> @min_epu16(<8 x i16> %a0, <8 x i16> %a1) {
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; CHECK-LABEL: min_epu16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminuw %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16>, <8 x i16>) nounwind readnone
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define <4 x i32> @max_epi32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: max_epi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxsd %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @min_epi32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: min_epi32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminsd %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @max_epu32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: max_epu32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pmaxud %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32>, <4 x i32>) nounwind readnone
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define <4 x i32> @min_epu32(<4 x i32> %a0, <4 x i32> %a1) {
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; CHECK-LABEL: min_epu32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pminud %xmm1, %xmm0
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; CHECK-NEXT: retl
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;
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%res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1)
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.sse41.pminud(<4 x i32>, <4 x i32>) nounwind readnone
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