forked from OSchip/llvm-project
210 lines
4.0 KiB
LLVM
210 lines
4.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
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; fold (shl (zext (lshr (A, X))), X) -> (zext (shl (lshr (A, X)), X))
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; Canolicalize the sequence shl/zext/lshr performing the zeroextend
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; as the last instruction of the sequence.
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; This will help DAGCombiner to identify and then fold the sequence
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; of shifts into a single AND.
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; This transformation is profitable if the shift amounts are the same
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; and if there is only one use of the zext.
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define i16 @fun1(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i16
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%shl = shl i16 %ext, 4
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ret i16 %shl
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}
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; CHECK-LABEL: @fun1
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i32 @fun2(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i32
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%shl = shl i32 %ext, 4
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ret i32 %shl
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}
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; CHECK-LABEL: @fun2
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i32 @fun3(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i32
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%shl = shl i32 %ext, 4
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ret i32 %shl
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}
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; CHECK-LABEL: @fun3
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun4(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun4
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun5(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun5
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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define i64 @fun6(i32 zeroext %v) {
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entry:
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%shr = lshr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun6
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; CHECK: and
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: ret
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; Don't fold the pattern if we use arithmetic shifts.
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define i64 @fun7(i8 zeroext %v) {
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entry:
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%shr = ashr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun7
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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define i64 @fun8(i16 zeroext %v) {
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entry:
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%shr = ashr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun8
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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define i64 @fun9(i32 zeroext %v) {
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entry:
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%shr = ashr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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ret i64 %shl
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}
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; CHECK-LABEL: @fun9
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; CHECK: sar
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; CHECK: shl
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; CHECK: ret
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; Don't fold the pattern if there is more than one use of the
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; operand in input to the shift left.
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define i64 @fun10(i8 zeroext %v) {
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entry:
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%shr = lshr i8 %v, 4
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%ext = zext i8 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun10
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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define i64 @fun11(i16 zeroext %v) {
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entry:
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%shr = lshr i16 %v, 4
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%ext = zext i16 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun11
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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define i64 @fun12(i32 zeroext %v) {
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entry:
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%shr = lshr i32 %v, 4
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%ext = zext i32 %shr to i64
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%shl = shl i64 %ext, 4
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%add = add i64 %shl, %ext
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ret i64 %add
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}
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; CHECK-LABEL: @fun12
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; CHECK: shr
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; CHECK: shl
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; CHECK: ret
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; PR17380
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; Make sure that the combined dags are legal if we run the DAGCombiner after
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; Legalization took place. The add instruction is redundant and increases by
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; one the number of uses of the zext. This prevents the transformation from
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; firing before dags are legalized and optimized.
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; Once the add is removed, the number of uses becomes one and therefore the
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; dags are canonicalized. After Legalization, we need to make sure that the
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; valuetype for the shift count is legal.
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; Verify also that we correctly fold the shl-shr sequence into an
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; AND with bitmask.
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define void @g(i32 %a) {
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%b = lshr i32 %a, 2
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%c = zext i32 %b to i64
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%d = add i64 %c, 1
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%e = shl i64 %c, 2
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tail call void @f(i64 %e)
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ret void
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}
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; CHECK-LABEL: @g
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; CHECK-NOT: shr
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; CHECK-NOT: shl
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; CHECK: and
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; CHECK-NEXT: jmp
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declare void @f(i64)
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