forked from OSchip/llvm-project
381 lines
9.9 KiB
LLVM
381 lines
9.9 KiB
LLVM
; Test 8-bit conditional stores that are presented as selects. The volatile
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; tests require z10, which use a branch instead of a LOCR.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
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declare void @foo(i8 *)
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; Test the simple case, with the loaded value first.
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define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f1:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f2:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %alt, i8 %orig
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store i8 %res, i8 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 32 bits, with the
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; loaded value first.
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define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = sext i8 %orig to i32
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%res = select i1 %cond, i32 %ext, i32 %alt
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%trunc = trunc i32 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f4:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = sext i8 %orig to i32
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%res = select i1 %cond, i32 %alt, i32 %ext
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%trunc = trunc i32 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 32 bits, with the
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; loaded value first.
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define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f5:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = zext i8 %orig to i32
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%res = select i1 %cond, i32 %ext, i32 %alt
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%trunc = trunc i32 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
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; CHECK-LABEL: f6:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = zext i8 %orig to i32
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%res = select i1 %cond, i32 %alt, i32 %ext
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%trunc = trunc i32 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; Test cases where the value is explicitly sign-extended to 64 bits, with the
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; loaded value first.
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define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = sext i8 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f8:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = sext i8 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; Test cases where the value is explicitly zero-extended to 64 bits, with the
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; loaded value first.
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define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f9:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = zext i8 %orig to i64
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%res = select i1 %cond, i64 %ext, i64 %alt
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%trunc = trunc i64 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; ...and with the loaded value second
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define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
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; CHECK-LABEL: f10:
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; CHECK-NOT: %r2
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; CHECK: bher %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%ext = zext i8 %orig to i64
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%res = select i1 %cond, i64 %alt, i64 %ext
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%trunc = trunc i64 %res to i8
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store i8 %trunc, i8 *%ptr
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ret void
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}
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; Check the high end of the STC range.
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define void @f11(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f11:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stc %r3, 4095(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4095
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check the next byte up, which should use STCY instead of STC.
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define void @f12(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f12:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stcy %r3, 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 4096
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check the high end of the STCY range.
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define void @f13(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f13:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stcy %r3, 524287(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 524287
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check the next byte up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f14(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f14:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, 524288
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 524288
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check the low end of the STCY range.
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define void @f15(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f15:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stcy %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 -524288
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check the next byte down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f16(i8 *%base, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f16:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: agfi %r2, -524289
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8, i8 *%base, i64 -524289
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check that STCY allows an index.
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define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f17:
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; CHECK-NOT: %r2
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; CHECK: blr %r14
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; CHECK-NOT: %r2
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; CHECK: stcy %r4, 4096(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %base, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i8 *
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; Check that volatile loads are not matched.
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define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f18:
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; CHECK: lb {{%r[0-5]}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stc {{%r[0-5]}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load volatile i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; ...likewise stores. In this case we should have a conditional load into %r3.
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define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
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; CHECK-LABEL: f19:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lb %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store volatile i8 %res, i8 *%ptr
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ret void
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}
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; Check that atomic loads are not matched. The transformation is OK for
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; the "unordered" case tested here, but since we don't try to handle atomic
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; operations at all in this context, it seems better to assert that than
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; to restrict the test to a stronger ordering.
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define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
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; FIXME: should use a normal load instead of CS.
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; CHECK-LABEL: f20:
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; CHECK: lb {{%r[0-9]+}}, 0(%r2)
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; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
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; CHECK: [[LABEL]]:
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; CHECK: stc {{%r[0-9]+}}, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load atomic i8 , i8 *%ptr unordered, align 1
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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ret void
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}
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; ...likewise stores.
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define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
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; FIXME: should use a normal store instead of CS.
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; CHECK-LABEL: f21:
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; CHECK: jhe [[LABEL:[^ ]*]]
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; CHECK: lb %r3, 0(%r2)
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; CHECK: [[LABEL]]:
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store atomic i8 %res, i8 *%ptr unordered, align 1
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ret void
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}
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; Try a frame index base.
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define void @f22(i8 %alt, i32 %limit) {
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; CHECK-LABEL: f22:
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; CHECK: brasl %r14, foo@PLT
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; CHECK-NOT: %r15
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; CHECK: jl [[LABEL:[^ ]*]]
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; CHECK-NOT: %r15
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; CHECK: stc {{%r[0-9]+}}, {{[0-9]+}}(%r15)
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; CHECK: [[LABEL]]:
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; CHECK: brasl %r14, foo@PLT
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; CHECK: br %r14
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%ptr = alloca i8
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call void @foo(i8 *%ptr)
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%cond = icmp ult i32 %limit, 420
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%orig = load i8 , i8 *%ptr
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%res = select i1 %cond, i8 %orig, i8 %alt
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store i8 %res, i8 *%ptr
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call void @foo(i8 *%ptr)
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ret void
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}
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