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Jim Grosbach c6f32b3295 ARM: Thumb add(sp plus register) asm constraints. 
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.

rdar://11219154

llvm-svn: 155748
 		2012-04-27 23:51:36 +00:00
..
ARM ARM: Thumb add(sp plus register) asm constraints. 2012-04-27 23:51:36 +00:00
AsmParser MC assembly parser handling for trailing comma in macro instantiation. 2012-04-16 21:18:49 +00:00
COFF Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
Disassembler Missed some register numbers. 2012-04-27 12:21:46 +00:00
ELF Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
MBlaze Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
MachO Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 2012-03-25 09:02:19 +00:00
Mips This patch fixes 3 problems: 2012-04-16 18:20:26 +00:00
X86 Add retw and lretw instructions. Also, fix Intel syntax parsing for all 2012-04-11 01:10:53 +00:00