llvm-project/llvm/test/CodeGen
Sanjay Patel 2bf82879bd [x86] split more 256-bit stores of concatenated vectors
As suggested in D62498 - collectConcatOps() matches both
concat_vectors and insert_subvector patterns, and we see
more test improvements by using the more general match.

llvm-svn: 362620
2019-06-05 16:40:57 +00:00
..
AArch64 [AArch64] FastISel: fix test to specify -fast-isel when -fast-isel-abort=1 is used. 2019-06-04 23:11:42 +00:00
AMDGPU [NFC][Codegen][AMDGPU] Autogenerate commute-shifts.ll test 2019-06-04 17:05:06 +00:00
ARC
ARM [NFC][Codegen] D62818 - also add tests with X being constant 2019-06-04 11:44:50 +00:00
AVR [AVR] Fix incorrect source regclass of LDWRdPtr 2019-06-03 02:31:07 +00:00
BPF [BPF] generate R_BPF_NONE relocation for BTF DataSec variables 2019-05-26 21:26:06 +00:00
Generic [IR] allow fast-math-flags on select of FP values 2019-05-22 15:50:46 +00:00
Hexagon UpdateTestChecks: hexagon support 2019-06-05 14:08:01 +00:00
Inputs
Lanai [DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952) 2019-06-04 11:06:21 +00:00
MIR [MIR-Canon] Don't do vreg skip for independent instructions if there are none. 2019-05-31 17:34:25 +00:00
MSP430 [AsmPrinter] refactor to support %c w/ GlobalAddress' 2019-04-26 18:45:04 +00:00
Mips [MIPS GlobalISel] Select fcmp 2019-06-05 14:03:13 +00:00
NVPTX SelectionDAG: accommodate atomic floating stores. 2019-05-10 11:23:04 +00:00
PowerPC [PowerPC] Collapse RLDICL/RLDICR into RLDIC when possible 2019-06-05 02:36:40 +00:00
RISCV [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
SPARC [DAGCombiner][X86][AArch64][SPARC][SystemZ] y - (x + C) -> (y - x) - C fold. Try 3 2019-05-30 20:37:18 +00:00
SystemZ [NFC] Update the test to check the endianness after the CodeGenPrepare instead of checking the assembly instructions. 2019-06-04 08:45:07 +00:00
Thumb [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
Thumb2 [ARM] Replace fp-only-sp and d16 with fp64 and d32. 2019-05-28 16:13:20 +00:00
WebAssembly [WebAssembly] Fix ISel crash on sext_inreg/extract type mismatch 2019-06-04 21:08:20 +00:00
WinCFGuard
WinEH
X86 [x86] split more 256-bit stores of concatenated vectors 2019-06-05 16:40:57 +00:00
XCore [AsmPrinter] refactor to support %c w/ GlobalAddress' 2019-04-26 18:45:04 +00:00