..
AsmParser
[RISCV] Change parseVTypeI function
2021-02-12 19:38:34 +08:00
Disassembler
[RISCV] Fix shared libs build
2021-02-09 06:14:25 -06:00
MCTargetDesc
[RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple.
2021-03-14 17:21:31 -07:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.h
[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
2021-03-16 10:02:35 -07:00
RISCV.td
[RISCV] Fix name of Zba extension (NFC)
2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp
[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
2021-03-16 10:02:35 -07:00
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
…
RISCVCleanupVSETVLI.cpp
[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli
2021-02-25 07:51:19 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp
[RISCV] Spilling for Zvlsseg registers.
2021-03-19 07:46:16 +08:00
RISCVFrameLowering.cpp
change rvv frame layout
2021-03-13 16:05:55 +08:00
RISCVFrameLowering.h
change rvv frame layout
2021-03-13 16:05:55 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Use selectImm for RV32. NFC
2021-03-23 08:57:15 -07:00
RISCVISelDAGToDAG.h
[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
2021-02-24 16:06:29 -08:00
RISCVISelLowering.cpp
[RISCV] Further optimize BUILD_VECTORs with repeated elements
2021-03-23 14:14:48 +00:00
RISCVISelLowering.h
[RISCV] Add support for fixed vector masked gather/scatter.
2021-03-22 10:17:30 -07:00
RISCVInstrFormats.td
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp
[RISCV] Spilling for Zvlsseg registers.
2021-03-19 07:46:16 +08:00
RISCVInstrInfo.h
[RISCV] Spilling for Zvlsseg registers.
2021-03-19 07:46:16 +08:00
RISCVInstrInfo.td
[RISCV] Use selectImm for RV32. NFC
2021-03-23 08:57:15 -07:00
RISCVInstrInfoA.td
[RISCV] Add explicit i64 types to RV64 isel patterns to stop tablegen from generating unneeded i32 patterns for RV32 HwMode.
2021-03-08 09:06:56 -08:00
RISCVInstrInfoB.td
[RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
2021-02-19 10:07:12 -08:00
RISCVInstrInfoC.td
[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td
[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
2021-02-24 16:06:29 -08:00
RISCVInstrInfoF.td
[RISCV] Use a ComplexPattern for zexti32 to match sexti32.
2021-02-24 16:06:29 -08:00
RISCVInstrInfoM.td
[RISCV] Update comment in RISCVInstrInfoM.td
2021-03-20 22:35:40 +00:00
RISCVInstrInfoV.td
[RISCV][MC] Fix nf encoding for vector ld/st whole register
2021-03-08 19:30:24 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Spilling for Zvlsseg registers.
2021-03-19 07:46:16 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Lower scalable vector masked loads to intrinsics to match fixed vectors and reduce isel patterns.
2021-03-19 10:39:35 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Optimize INSERT_VECTOR_ELT sequences
2021-03-12 09:13:38 +00:00
RISCVInstrInfoZfh.td
[RISCV] Add HasStdExtD predicate to copysign from double and to double patterns
2021-03-24 14:29:23 +08:00
RISCVInstructionSelector.cpp
RISCV: Avoid GlobalISel build break in a future patch
2020-07-13 14:01:57 -04:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
[RISCV] Support clang -fpatchable-function-entry && GNU function attribute 'patchable_function_entry'
2021-03-16 10:02:35 -07:00
RISCVMachineFunctionInfo.h
change rvv frame layout
2021-03-13 16:05:55 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] remove redundant instruction when eliminate frame index
2021-03-21 18:54:00 +08:00
RISCVRegisterInfo.h
[RISCV] Improve register allocation around vector masks
2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td
[RISCV] Support inline asm for vector instructions.
2021-03-15 11:02:18 +08:00
RISCVSchedRocket.td
[RISCV] Add scheduler classes to Zfh instructions.
2021-03-22 20:30:09 -07:00
RISCVSchedSiFive7.td
[RISCV] Add scheduler classes to Zfh instructions.
2021-03-22 20:30:09 -07:00
RISCVSchedule.td
[RISCV] Add scheduler classes to Zfh instructions.
2021-03-22 20:30:09 -07:00
RISCVSubtarget.cpp
[RISCV] Give an explicit error if 'generic' CPU is passed instead of 'generic-rv32' or 'generic-rv64'. Validate 64Bit feature against the triple.
2021-03-14 17:21:31 -07:00
RISCVSubtarget.h
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td
[RISCV] Enable the use of the old mucounteren name
2020-08-17 13:11:49 +01:00
RISCVTargetMachine.cpp
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
2021-03-02 12:55:51 -08:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Add TTI support for cpop with Zbb
2021-03-24 10:58:42 -07:00
RISCVTargetTransformInfo.h
[RISCV] Add TTI support for cpop with Zbb
2021-03-24 10:58:42 -07:00
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