Dmitry Preobrazhensky 933ebc4078 [AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64 ... See bug 45925: https://bugs.llvm.org/show_bug.cgi?id=45925 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D80287		2020-05-22 14:11:31 +03:00
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AArch64	[AArch64][GlobalISel] Add a post-legalizer combiner with a very simple combine.	2020-05-21 18:47:32 -07:00
AMDGPU	[AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64	2020-05-22 14:11:31 +03:00
ARC	…
ARM	Revert "[ARM] Improve codegen of volatile load/store of i64"	2020-05-22 11:01:57 +01:00
AVR	[AVR] Fix I/O instructions on XMEGA	2020-05-17 19:46:09 +12:00
BPF	[BPF] Return fail if disassembled insn registers out of range	2020-05-18 18:53:23 -07:00
Generic	[MachineDebugify] Insert synthetic DBG_VALUE instructions	2020-04-22 17:03:39 -07:00
Hexagon	[ModuloSchedule] Fix epilogue peeling with illegal phi.	2020-05-07 10:04:05 -07:00
Inputs	…
Lanai	…
MIR	[AMDGPU] Avoid hard-coded line numbers in error message checks	2020-04-23 21:06:09 +01:00
MSP430	…
Mips	[llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC	2020-05-21 09:29:27 -06:00
NVPTX	…
PowerPC	[NFC][Test] Add test coverage for fsqrt on PowerPC	2020-05-22 10:59:27 +00:00
RISCV	[RISCV] Support Constant Pools in Load/Store Peephole	2020-05-11 19:20:38 +01:00
SPARC	…
SystemZ	[SystemZ] Eliminate the need to create a zero vector by reusing the VPERM mask.	2020-05-19 09:37:19 +02:00
Thumb	[ARM] Don't shrink STM if it would cause an unknown base register store	2020-04-22 14:50:42 +01:00
Thumb2	[CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias	2020-05-21 23:02:54 +02:00
VE	[VE] Update branch instructions	2020-04-28 09:41:01 +02:00
WebAssembly	[WebAssembly] Fix bug in custom shuffle combine	2020-05-19 12:54:15 -07:00
WinCFGuard	…
WinEH	…
X86	Don't jump to landing pads in Control Flow Optimizer	2020-05-21 15:19:10 -07:00
XCore	…