llvm-project/llvm/test/Analysis/CostModel/X86
Craig Topper 35625464c6 [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2
We seem to be inheriting the cost from sse4.1. But if we have 256-bit registers we should be able to do this with just one extract to split the 16i16 and two v8i16->v8i32 operations so our cost should be 3 not 4.

Differential Revision: https://reviews.llvm.org/D73646
2020-01-29 15:52:10 -08:00
..
aggregates.ll [CostModel] Model all `extractvalue`s as free. 2019-08-29 11:50:30 +00:00
alternate-shuffle-cost.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
arith-fix.ll [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 2020-01-29 15:52:10 -08:00
arith-fma.ll
arith-fp.ll [CostModel] Add really basic support for being able to query the cost of the FNeg instruction. 2019-05-28 04:09:18 +00:00
arith-overflow.ll [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 2020-01-29 15:52:10 -08:00
arith-ssat.ll [CostModel][X86] Fix SLM <2 x i64> icmp costs 2019-09-26 10:14:38 +00:00
arith-usat.ll [CostModel][X86] Fix SLM <2 x i64> icmp costs 2019-09-26 10:14:38 +00:00
arith.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
bitreverse.ll
bswap.ll
cast.ll [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 2020-01-29 15:52:10 -08:00
costmodel.ll
ctlz.ll [CostModel][X86] Add CTLZ scalar costs 2019-10-14 16:30:17 +00:00
ctpop.ll [CostModel][X86] Add CTPOP scalar costs (PR43656) 2019-10-14 14:07:43 +00:00
cttz.ll
div.ll
extend.ll [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 2020-01-29 15:52:10 -08:00
fcmp.ll [CostModel][X86] Add explicit fcmp costs for pre-SSE42 targets 2019-01-20 13:21:43 +00:00
fptosi.ll [x86] add cost model special-case for insert/extract from element 0 2019-12-06 13:50:25 -05:00
fptoui.ll [x86] add cost model special-case for insert/extract from element 0 2019-12-06 13:50:25 -05:00
fround.ll
fshl.ll [CostModel][X86] Fix SLM <2 x i64> icmp costs 2019-09-26 10:14:38 +00:00
fshr.ll [CostModel][X86] Fix SLM <2 x i64> icmp costs 2019-09-26 10:14:38 +00:00
gep.ll
i32.ll
icmp.ll [CostModel][X86] Fix SLM <2 x i64> icmp costs 2019-09-26 10:14:38 +00:00
insert-extract-at-zero.ll
interleave-load-i32.ll
interleave-store-i32.ll
interleaved-load-float.ll
interleaved-load-i8.ll
interleaved-load-store-double.ll
interleaved-load-store-i64.ll
interleaved-store-i8.ll
intrinsic-cost.ll
lit.local.cfg [lit] Delete empty lines at the end of lit.local.cfg NFC 2019-06-17 09:51:07 +00:00
load_store.ll
loop_v2.ll
masked-intrinsic-cost.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
min-legal-vector-width.ll [X86] Fix the cost model for v16i16->v16i32 zero_extend/sign_extend with AVX2 2020-01-29 15:52:10 -08:00
reduce-add.ll [CostModel][X86] Improve add vXi64 + fadd vXf64 reduction tests for SLM 2019-11-06 17:55:38 +00:00
reduce-and.ll [X86] Lower the cost of avx512 horizontal bool and/or reductions to 2*log2(bitwidth)+1 for legal types. 2019-11-04 22:58:04 -08:00
reduce-mul.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-or.ll [X86] Lower the cost of avx512 horizontal bool and/or reductions to 2*log2(bitwidth)+1 for legal types. 2019-11-04 22:58:04 -08:00
reduce-smax.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-smin.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-umax.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-umin.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduce-xor.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
reduction.ll [CostModel][X86] Improve add vXi64 + fadd vXf64 reduction tests for SLM 2019-11-06 17:55:38 +00:00
rem.ll
scalarize.ll
shuffle-broadcast.ll
shuffle-extract_subvector.ll [x86] add cost model special-case for insert/extract from element 0 2019-12-06 13:50:25 -05:00
shuffle-insert_subvector.ll
shuffle-reverse.ll
shuffle-single-src.ll
shuffle-transpose.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
shuffle-two-src.ll
sitofp.ll [X86] Lower the cost of v2i32->v2f64 sint_to_fp under vector widening legalization. 2019-08-22 08:18:45 +00:00
slm-arith-costs.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
sse-itoi.ll
strided-load-i8.ll
strided-load-i16.ll
strided-load-i32.ll
strided-load-i64.ll
testshiftashr.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
testshiftlshr.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
testshiftshl.ll Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." 2019-08-07 16:24:26 +00:00
tiny.ll
trunc.ll [Cost][X86] Add more missing vector truncation costs 2019-09-22 16:46:15 +00:00
uitofp.ll [CostModel][X86] Add missing scalar i64->f32 uitofp costs 2020-01-06 13:17:02 +00:00
uniformshift.ll
vdiv-cost.ll
vector-extract.ll [x86] add cost model special-case for insert/extract from element 0 2019-12-06 13:50:25 -05:00
vector-insert.ll [CostModel][X86] Add tests for insertelement to non-immediate vector element indices 2019-10-09 12:36:34 +00:00
vector_gep.ll
vectorized-loop.ll
vselect-cost.ll [CostModel][X86] Add explicit vector select costs 2019-01-20 13:55:01 +00:00
vshift-ashr-cost.ll
vshift-lshr-cost.ll
vshift-shl-cost.ll