llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_scalar_add_big() {
  entry:
    ret void
  }
  define void @test_scalar_add_big_nonpow2() {
  entry:
    ret void
  }
  define void @test_scalar_add_small() {
  entry:
    ret void
  }
  define void @test_vector_add() {
  entry:
    ret void
  }
  define void @test_vector_add_nonpow2() {
  entry:
    ret void
  }  
...

---
name:            test_scalar_add_big
body: |
  bb.0.entry:
    liveins: $x0, $x1, $x2, $x3

    ; CHECK-LABEL: name: test_scalar_add_big
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
    ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
    ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY2]], [[TRUNC]]
    ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
    ; CHECK: $x0 = COPY [[UADDE]](s64)
    ; CHECK: $x1 = COPY [[UADDE2]](s64)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s64) = COPY $x2
    %3:_(s64) = COPY $x3
    %4:_(s128) = G_MERGE_VALUES %0, %1
    %5:_(s128) = G_MERGE_VALUES %2, %3
    %6:_(s128) = G_ADD %4, %5
    %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
    $x0 = COPY %7
    $x1 = COPY %8  
...

---
name:            test_scalar_add_big_nonpow2
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
  - { id: 9, class: _ }
body: |
  bb.0.entry:
    liveins: $x0, $x1, $x2, $x3
    ; CHECK-LABEL: name: test_scalar_add_big_nonpow2
    ; CHECK-NOT: G_MERGE_VALUES
    ; CHECK-NOT: G_UNMERGE_VALUES
    ; CHECK-DAG: [[CARRY0_32:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK-DAG: [[CARRY0:%[0-9]+]]:_(s1) = G_TRUNC [[CARRY0_32]]
    ; CHECK: [[RES_LO:%[0-9]+]]:_(s64), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE %0, %1, [[CARRY0]]
    ; CHECK: [[RES_MI:%[0-9]+]]:_(s64), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE %1, %2, [[CARRY1]]
    ; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
    ; CHECK-NOT: G_MERGE_VALUES
    ; CHECK-NOT: G_UNMERGE_VALUES
    ; CHECK: $x0 = COPY [[RES_LO]]
    ; CHECK: $x1 = COPY [[RES_MI]]
    ; CHECK: $x2 = COPY [[RES_HI]]

    %0(s64) = COPY $x0
    %1(s64) = COPY $x1
    %2(s64) = COPY $x2
    %3(s64) = COPY $x3
    %4(s192) = G_MERGE_VALUES %0, %1, %2
    %5(s192) = G_MERGE_VALUES %1, %2, %3
    %6(s192) = G_ADD %4, %5
    %7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
    $x0 = COPY %7
    $x1 = COPY %8
    $x2 = COPY %9  
...

---
name:            test_scalar_add_small
body: |
  bb.0.entry:
    liveins: $x0, $x1, $x2, $x3

    ; CHECK-LABEL: name: test_scalar_add_small
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
    ; CHECK: $x0 = COPY [[ANYEXT]](s64)
    %0:_(s64) = COPY $x0
    %1:_(s64) = COPY $x1
    %2:_(s8) = G_TRUNC %0
    %3:_(s8) = G_TRUNC %1
    %4:_(s8) = G_ADD %2, %3
    %5:_(s64) = G_ANYEXT %4
    $x0 = COPY %5  
...

---
name:            test_vector_add
body: |
  bb.0.entry:
    liveins: $q0, $q1, $q2, $q3

    ; CHECK-LABEL: name: test_vector_add
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
    ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
    ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY2]]
    ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
    ; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
    ; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s64>) = COPY $q2
    %3:_(<2 x s64>) = COPY $q3
    %4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
    %5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
    %6:_(<4 x s64>) = G_ADD %4, %5
    %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
    $q0 = COPY %7
    $q1 = COPY %8  
...
---
name:            test_vector_add_nonpow2
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
  - { id: 9, class: _ }
body: |
  bb.0.entry:
    liveins: $q0, $q1, $q2, $q3
    ; CHECK-LABEL: name: test_vector_add_nonpow2
    ; CHECK-NOT: G_EXTRACT
    ; CHECK-NOT: G_SEQUENCE
    ; CHECK: [[RES_LO:%[0-9]+]]:_(<2 x s64>) = G_ADD %0, %1
    ; CHECK: [[RES_MI:%[0-9]+]]:_(<2 x s64>) = G_ADD %1, %2
    ; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
    ; CHECK-NOT: G_EXTRACT
    ; CHECK-NOT: G_SEQUENCE
    ; CHECK: $q0 = COPY [[RES_LO]]
    ; CHECK: $q1 = COPY [[RES_MI]]
    ; CHECK: $q2 = COPY [[RES_HI]]

    %0(<2 x s64>) = COPY $q0
    %1(<2 x s64>) = COPY $q1
    %2(<2 x s64>) = COPY $q2
    %3(<2 x s64>) = COPY $q3
    %4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
    %5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
    %6(<6 x s64>) = G_ADD %4, %5
    %7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
    $q0 = COPY %7
    $q1 = COPY %8
    $q2 = COPY %9  
...