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llvm-project/llvm/lib/Target/RISCV
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Alex Bradbury 9d3f12501a [RISCV] Add common fixups and relocations 
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to 
ensure the appropriate fixups and relocations are generated. I've added an 
instruction format field which is used in RISCVMCCodeEmitter to, for 
instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup 
(RISC-V has two 12-bit immediate encodings depending on the instruction 
type).

Differential Revision: https://reviews.llvm.org/D23568

llvm-svn: 314389
 		2017-09-28 08:26:24 +00:00
..
AsmParser [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
Disassembler [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
InstPrinter [RISCV] Add support for all RV32I instructions 2017-09-17 14:27:35 +00:00
MCTargetDesc [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
TargetInfo [RISCV] Add bare-bones RISC-V MCTargetDesc 2016-11-01 23:47:30 +00:00
CMakeLists.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
LLVMBuild.txt [RISCV] Add support for disassembly 2017-09-17 14:36:28 +00:00
RISCV.td [RISCV] Add basic RISCVAsmParser 2017-08-08 14:32:35 +00:00
RISCVInstrFormats.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVInstrInfo.td [RISCV] Add common fixups and relocations 2017-09-28 08:26:24 +00:00
RISCVRegisterInfo.td
…
RISCVTargetMachine.cpp Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00
RISCVTargetMachine.h Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00