forked from OSchip/llvm-project
156 lines
6.5 KiB
LLVM
156 lines
6.5 KiB
LLVM
; RUN: llc -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; Test addressing modes when the scratch base is not a frame index.
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; GCN-LABEL: {{^}}store_private_offset_i8:
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; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @store_private_offset_i8() #0 {
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store volatile i8 5, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i16:
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; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @store_private_offset_i16() #0 {
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store volatile i16 5, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i32:
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; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @store_private_offset_i32() #0 {
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store volatile i32 5, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_v2i32:
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; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @store_private_offset_v2i32() #0 {
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store volatile <2 x i32> <i32 5, i32 10>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_v4i32:
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; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @store_private_offset_v4i32() #0 {
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store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i8:
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @load_private_offset_i8() #0 {
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%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}sextload_private_offset_i8:
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; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
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%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
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%sextload = sext i8 %load to i32
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store i32 %sextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}zextload_private_offset_i8:
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; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
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%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
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%zextload = zext i8 %load to i32
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store i32 %zextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i16:
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; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @load_private_offset_i16() #0 {
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%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}sextload_private_offset_i16:
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; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
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%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
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%sextload = sext i16 %load to i32
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store i32 %sextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}zextload_private_offset_i16:
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; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
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%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
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%zextload = zext i16 %load to i32
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store i32 %zextload, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_i32:
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; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @load_private_offset_i32() #0 {
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%load = load volatile i32, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_v2i32:
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; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @load_private_offset_v2i32() #0 {
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%load = load volatile <2 x i32>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}load_private_offset_v4i32:
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; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], 0 offset:8
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define amdgpu_kernel void @load_private_offset_v4i32() #0 {
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%load = load volatile <4 x i32>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:
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; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], 0 offset:4095
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define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {
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store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4095 to i8 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1:
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; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
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; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], 0 offen{{$}}
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define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {
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store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4096 to i8 addrspace(5)*)
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ret void
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}
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; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2:
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; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
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; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], 0 offen offset:1{{$}}
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define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
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store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4097 to i8 addrspace(5)*)
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ret void
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}
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; MUBUF used for stack access has bounds checking enabled before gfx9,
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; so a possibly negative base index can't be used for the vgpr offset.
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; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr:
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; SICIVI: v_add_{{i|u}}32_e32 [[ADDR0:v[0-9]+]], vcc, 4
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; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR0]]
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; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
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; GFX9: v_add_u32_e32 [[ADDR:v[0-9]+]], 4,
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; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, 0 offen offset:32
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define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 {
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%alloca = alloca [16 x i32], align 4, addrspace(5)
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%vaddr = load volatile i32, i32 addrspace(1)* undef
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%vaddr.off = add i32 %vaddr, 8
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%gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %vaddr.off
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store volatile i32 9, i32 addrspace(5)* %gep
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ret void
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}
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attributes #0 = { nounwind }
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