llvm-project/llvm/test/CodeGen
Nirav Dave 1241dcb3cf Bias physical register immediate assignments
The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.

This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out-of-registers
assertion (PR39391).

Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.

Reviewers: MatzeB, qcolombet, myatsina, pcc

Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya,
  javed.absar, arphaman, jfb, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D54218

llvm-svn: 346894
2018-11-14 21:11:53 +00:00
..
AArch64 [ARM64] [Windows] Handle funclets 2018-11-09 23:33:30 +00:00
AMDGPU Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
ARC
ARM [CodeGen] Fix forward scan in MachineBasicBlock::computeRegisterLiveness. 2018-11-14 00:39:29 +00:00
AVR [AVR] Reorder the CHECK lines in directmem.ll to match current trunk 2018-11-09 23:17:59 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic [IR] Add a dedicated FNeg IR Instruction 2018-11-13 18:15:47 +00:00
Hexagon [Hexagon] Implement noreturn optimization 2018-11-09 18:16:24 +00:00
Inputs
Lanai
MIR [Power9] Allow gpr callee saved spills in prologue to vectors registers 2018-11-09 16:36:24 +00:00
MSP430 Revert "[MSP430] Add MC layer" 2018-11-08 16:21:29 +00:00
Mips [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars 2018-11-09 18:04:34 +00:00
NVPTX
Nios2
PowerPC [PowerPC] Enhance the selection(ISD::VSELECT) of vector type 2018-11-14 02:34:45 +00:00
RISCV [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SystemZ] Increase the number of VLREPs 2018-11-13 08:37:09 +00:00
Thumb [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
Thumb2 [ARM] Enable spilling of the hGPR register class in Thumb2 2018-11-08 13:02:10 +00:00
WebAssembly [WebAssembly] Add support for the event section 2018-11-14 02:46:21 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
X86 Bias physical register immediate assignments 2018-11-14 21:11:53 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00