forked from OSchip/llvm-project
104 lines
5.0 KiB
LLVM
104 lines
5.0 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: v{{[0-9]+}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
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; CHECK: }
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; CHECK: {
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; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: }
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; CHECK: {
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; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
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target triple = "hexagon"
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@ZERO = global <16 x i32> zeroinitializer, align 64
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define void @fred(i16* nocapture readonly %a0, i32 %a1, i32 %a2, i16* nocapture %a3) #0 {
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b4:
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%v5 = bitcast i16* %a0 to <16 x i32>*
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%v6 = getelementptr inbounds i16, i16* %a0, i32 %a1
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%v7 = bitcast i16* %v6 to <16 x i32>*
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%v8 = mul nsw i32 %a1, 2
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%v9 = getelementptr inbounds i16, i16* %a0, i32 %v8
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%v10 = bitcast i16* %v9 to <16 x i32>*
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%v11 = load <16 x i32>, <16 x i32>* %v5, align 64, !tbaa !1
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%v12 = load <16 x i32>, <16 x i32>* %v7, align 64, !tbaa !1
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%v13 = load <16 x i32>, <16 x i32>* %v10, align 64, !tbaa !1
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%v14 = load <16 x i32>, <16 x i32>* @ZERO, align 64, !tbaa !1
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%v15 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v14, <16 x i32> %v14)
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%v16 = sdiv i32 %a2, 32
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%v17 = icmp sgt i32 %a2, 31
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br i1 %v17, label %b18, label %b66
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b18: ; preds = %b4
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%v19 = add i32 %v8, 32
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%v20 = add i32 %a1, 32
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%v21 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v12, <16 x i32> %v12)
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%v22 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v11, <16 x i32> %v13)
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%v23 = getelementptr inbounds i16, i16* %a0, i32 %v19
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%v24 = getelementptr inbounds i16, i16* %a0, i32 %v20
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%v25 = getelementptr inbounds i16, i16* %a0, i32 32
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%v26 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v11, <16 x i32> %v13)
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%v27 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v22, <16 x i32> %v21)
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%v28 = bitcast i16* %v23 to <16 x i32>*
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%v29 = bitcast i16* %v24 to <16 x i32>*
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%v30 = bitcast i16* %v25 to <16 x i32>*
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%v31 = bitcast i16* %a3 to <16 x i32>*
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br label %b32
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b32: ; preds = %b32, %b18
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%v33 = phi i32 [ 0, %b18 ], [ %v63, %b32 ]
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%v34 = phi <16 x i32>* [ %v31, %b18 ], [ %v62, %b32 ]
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%v35 = phi <16 x i32>* [ %v28, %b18 ], [ %v46, %b32 ]
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%v36 = phi <16 x i32>* [ %v29, %b18 ], [ %v44, %b32 ]
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%v37 = phi <16 x i32>* [ %v30, %b18 ], [ %v42, %b32 ]
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%v38 = phi <16 x i32> [ %v15, %b18 ], [ %v39, %b32 ]
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%v39 = phi <16 x i32> [ %v26, %b18 ], [ %v56, %b32 ]
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%v40 = phi <16 x i32> [ %v27, %b18 ], [ %v51, %b32 ]
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%v41 = phi <16 x i32> [ %v15, %b18 ], [ %v40, %b32 ]
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%v42 = getelementptr inbounds <16 x i32>, <16 x i32>* %v37, i32 1
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%v43 = load <16 x i32>, <16 x i32>* %v37, align 64, !tbaa !1
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%v44 = getelementptr inbounds <16 x i32>, <16 x i32>* %v36, i32 1
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%v45 = load <16 x i32>, <16 x i32>* %v36, align 64, !tbaa !1
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%v46 = getelementptr inbounds <16 x i32>, <16 x i32>* %v35, i32 1
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%v47 = load <16 x i32>, <16 x i32>* %v35, align 64, !tbaa !1
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%v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v43, <16 x i32> %v47)
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%v49 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v45, <16 x i32> %v45)
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%v50 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v40, <16 x i32> %v41, i32 62)
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%v51 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v48, <16 x i32> %v49)
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%v52 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v51, <16 x i32> %v40, i32 2)
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%v53 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v50, <16 x i32> %v52)
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%v54 = getelementptr inbounds <16 x i32>, <16 x i32>* %v34, i32 1
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store <16 x i32> %v53, <16 x i32>* %v34, align 64, !tbaa !1
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%v55 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v39, <16 x i32> %v38, i32 62)
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%v56 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v43, <16 x i32> %v47)
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%v57 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v56, <16 x i32> %v39, i32 2)
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%v58 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v39)
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%v59 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v58, <16 x i32> %v55)
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%v60 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v59, <16 x i32> %v57)
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%v61 = tail call <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32> %v60)
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%v62 = getelementptr inbounds <16 x i32>, <16 x i32>* %v34, i32 2
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store <16 x i32> %v61, <16 x i32>* %v54, align 64, !tbaa !1
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%v63 = add nsw i32 %v33, 1
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%v64 = icmp slt i32 %v63, %v16
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br i1 %v64, label %b32, label %b65
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b65: ; preds = %b32
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br label %b66
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b66: ; preds = %b65, %b4
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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