forked from OSchip/llvm-project
141 lines
3.8 KiB
C++
141 lines
3.8 KiB
C++
//===-- tsan_rtl.h ----------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is a part of ThreadSanitizer (TSan), a race detector.
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//
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// Atomic operations. For now implies IA-32/Intel64.
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//===----------------------------------------------------------------------===//
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#ifndef TSAN_ATOMIC_H
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#define TSAN_ATOMIC_H
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#include "tsan_defs.h"
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namespace __tsan {
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const int kCacheLineSize = 64;
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enum memory_order {
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memory_order_relaxed = 1 << 0,
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memory_order_consume = 1 << 1,
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memory_order_acquire = 1 << 2,
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memory_order_release = 1 << 3,
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memory_order_acq_rel = 1 << 4,
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memory_order_seq_cst = 1 << 5,
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};
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struct atomic_uint32_t {
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typedef u32 Type;
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volatile Type val_dont_use;
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};
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struct atomic_uint64_t {
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typedef u64 Type;
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volatile Type val_dont_use;
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};
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struct atomic_uintptr_t {
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typedef uptr Type;
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volatile Type val_dont_use;
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};
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INLINE void atomic_signal_fence(memory_order) {
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__asm__ __volatile__("" ::: "memory");
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}
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INLINE void atomic_thread_fence(memory_order) {
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__asm__ __volatile__("mfence" ::: "memory");
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}
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INLINE void proc_yield(int cnt) {
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__asm__ __volatile__("" ::: "memory");
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for (int i = 0; i < cnt; i++)
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__asm__ __volatile__("pause");
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__asm__ __volatile__("" ::: "memory");
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}
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template<typename T>
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INLINE typename T::Type atomic_load(
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const volatile T *a, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_consume
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| memory_order_acquire | memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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typename T::Type v;
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if (mo == memory_order_relaxed) {
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v = a->val_dont_use;
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} else {
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atomic_signal_fence(memory_order_seq_cst);
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v = a->val_dont_use;
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atomic_signal_fence(memory_order_seq_cst);
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}
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return v;
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}
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template<typename T>
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INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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DCHECK(mo & (memory_order_relaxed | memory_order_release
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| memory_order_seq_cst));
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DCHECK(!((uptr)a % sizeof(*a)));
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if (mo == memory_order_relaxed) {
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a->val_dont_use = v;
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} else {
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atomic_signal_fence(memory_order_seq_cst);
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a->val_dont_use = v;
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atomic_signal_fence(memory_order_seq_cst);
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}
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if (mo == memory_order_seq_cst)
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atomic_thread_fence(memory_order_seq_cst);
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}
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template<typename T>
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INLINE typename T::Type atomic_fetch_add(volatile T *a,
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typename T::Type v, memory_order mo) {
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(void)mo;
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DCHECK(!((uptr)a % sizeof(*a)));
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return __sync_fetch_and_add(&a->val_dont_use, v);
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}
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template<typename T>
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INLINE typename T::Type atomic_fetch_sub(volatile T *a,
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typename T::Type v, memory_order mo) {
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(void)mo;
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DCHECK(!((uptr)a % sizeof(*a)));
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return __sync_fetch_and_add(&a->val_dont_use, -v);
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}
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INLINE uptr atomic_exchange(volatile atomic_uintptr_t *a, uptr v,
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memory_order mo) {
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__asm__ __volatile__("xchg %1, %0" : "+r"(v), "+m"(*a) : : "memory", "cc");
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return v;
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}
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template<typename T>
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INLINE bool atomic_compare_exchange_strong(volatile T *a,
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typename T::Type *cmp,
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typename T::Type xchg,
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memory_order mo) {
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typedef typename T::Type Type;
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Type cmpv = *cmp;
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Type prev = __sync_val_compare_and_swap(&a->val_dont_use, cmpv, xchg);
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if (prev == cmpv)
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return true;
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*cmp = prev;
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return false;
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}
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INLINE bool atomic_compare_exchange_weak(volatile atomic_uintptr_t *a,
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uptr *cmp, uptr xchg,
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memory_order mo) {
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return atomic_compare_exchange_strong(a, cmp, xchg, mo);
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}
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} // namespace __tsan
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#endif // TSAN_ATOMIC_H
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