forked from OSchip/llvm-project
375 lines
13 KiB
C++
375 lines
13 KiB
C++
//===------ LeonPasses.cpp - Define passes specific to LEON ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "LeonPasses.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char &ID)
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: MachineFunctionPass(ID) {}
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LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID)
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: MachineFunctionPass(ID) {}
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int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr &MI,
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int OperandIndex) {
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if (MI.getNumOperands() > 0) {
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if (OperandIndex == LAST_OPERAND) {
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OperandIndex = MI.getNumOperands() - 1;
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}
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if (MI.getNumOperands() > (unsigned)OperandIndex &&
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MI.getOperand(OperandIndex).isReg()) {
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return (int)MI.getOperand(OperandIndex).getReg();
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}
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}
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static int NotFoundIndex = -10;
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// Return a different number each time to avoid any comparisons between the
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// values returned.
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NotFoundIndex -= 10;
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return NotFoundIndex;
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}
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// finds a new free FP register
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// checks also the AllocatedRegisters vector
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int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo &MRI) {
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for (int RegisterIndex = SP::F0; RegisterIndex <= SP::F31; ++RegisterIndex) {
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if (!MRI.isPhysRegUsed(RegisterIndex) &&
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!is_contained(UsedRegisters, RegisterIndex)) {
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return RegisterIndex;
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}
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}
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return -1;
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}
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//*****************************************************************************
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//**** InsertNOPLoad pass
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//*****************************************************************************
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// This pass fixes the incorrectly working Load instructions that exists for
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// some earlier versions of the LEON processor line. NOP instructions must
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// be inserted after the load instruction to ensure that the Load instruction
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// behaves as expected for these processors.
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//
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// This pass inserts a NOP after any LD or LDF instruction.
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//
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char InsertNOPLoad::ID = 0;
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InsertNOPLoad::InsertNOPLoad(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool InsertNOPLoad::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixFSMULD pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FSMULD instruction that exists for
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// some earlier versions of the LEON processor line.
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//
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// The pass should convert the FSMULD operands to double precision in scratch
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// registers, then calculate the result with the FMULD instruction. Therefore,
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// the pass should replace operations of the form:
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// fsmuld %f20,%f21,%f8
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// with the sequence:
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// fstod %f20,%f0
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// fstod %f21,%f2
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// fmuld %f0,%f2,%f8
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//
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char FixFSMULD::ID = 0;
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FixFSMULD::FixFSMULD(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
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bool FixFSMULD::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) {
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// take the registers from fsmuld %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
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Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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// Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX ||
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ScratchReg2Index == UNASSIGNED_INDEX) {
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errs() << "Cannot allocate free scratch registers for the FixFSMULD "
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"pass."
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<< "\n";
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} else {
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// create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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// create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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// create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** ReplaceFMULS pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FMULS instruction that exists for
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// some earlier versions of the LEON processor line.
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//
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// This pass converts the FMULS operands to double precision in scratch
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// registers, then calculates the result with the FMULD instruction.
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// The pass should replace operations of the form:
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// fmuls %f20,%f21,%f8
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// with the sequence:
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// fstod %f20,%f0
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// fstod %f21,%f2
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// fmuld %f0,%f2,%f8
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//
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char ReplaceFMULS::ID = 0;
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ReplaceFMULS::ReplaceFMULS(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool ReplaceFMULS::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FMULS && MI.getNumOperands() == 3) {
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// take the registers from fmuls %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX &&
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Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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// Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX ||
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ScratchReg2Index == UNASSIGNED_INDEX) {
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errs() << "Cannot allocate free scratch registers for the "
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"ReplaceFMULS pass."
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<< "\n";
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} else {
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// create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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// create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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// create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** DetectRoundChange pass
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//*****************************************************************************
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// To prevent any explicit change of the default rounding mode, this pass
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// detects any call of the fesetround function.
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// A warning is generated to ensure the user knows this has happened.
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//
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// Detects an erratum in UT699 LEON 3 processor
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char DetectRoundChange::ID = 0;
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DetectRoundChange::DetectRoundChange(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool DetectRoundChange::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (Opcode == SP::CALL && MI.getNumOperands() > 0) {
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MachineOperand &MO = MI.getOperand(0);
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if (MO.isGlobal()) {
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StringRef FuncName = MO.getGlobal()->getName();
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if (FuncName.compare_lower("fesetround") == 0) {
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errs() << "Error: You are using the detectroundchange "
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"option to detect rounding changes that will "
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"cause LEON errata. The only way to fix this "
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"is to remove the call to fesetround from "
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"the source code.\n";
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}
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixAllFDIVSQRT pass
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//*****************************************************************************
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// This pass fixes the incorrectly working FDIVx and FSQRTx instructions that
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// exist for some earlier versions of the LEON processor line. Five NOP
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// instructions need to be inserted after these instructions to ensure the
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// correct result is placed in the destination registers before they are used.
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//
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// This pass implements two fixes:
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// 1) fixing the FSQRTS and FSQRTD instructions.
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// 2) fixing the FDIVS and FDIVD instructions.
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//
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// FSQRTS and FDIVS are converted to FDIVD and FSQRTD respectively earlier in
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// the pipeline when this option is enabled, so this pass needs only to deal
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// with the changes that still need implementing for the "double" versions
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// of these instructions.
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//
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char FixAllFDIVSQRT::ID = 0;
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FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm)
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: LEONMachineFunctionPass(tm, ID) {}
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bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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// Note: FDIVS and FSQRTS cannot be generated when this erratum fix is
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// switched on so we don't need to check for them here. They will
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// already have been converted to FSQRTD or FDIVD earlier in the
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// pipeline.
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if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
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for (int InsertedCount = 0; InsertedCount < 5; InsertedCount++)
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BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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for (int InsertedCount = 0; InsertedCount < 28; InsertedCount++)
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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return Modified;
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}
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