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llvm-project/llvm/test/CodeGen/MIR
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Saleem Abdulrasool 4c6c4e2bbb tests: tweak MIR for ARM tests to correct MI issues 
The Machine Instruction Verifier flagged some issues in the serialized MIR.
Adjust the input to correct them.

Fixes the remaining portion of PR27480.

llvm-svn: 267578
 		2016-04-26 17:54:21 +00:00
..
AArch64 [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth() 2016-03-31 20:53:47 +00:00
AMDGPU When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
ARM tests: tweak MIR for ARM tests to correct MI issues 2016-04-26 17:54:21 +00:00
Generic When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
Mips When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
NVPTX When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
PowerPC When printing MIR, output to errs() rather than outs(). 2016-02-19 00:18:46 +00:00
X86 [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00