forked from OSchip/llvm-project
269 lines
7.1 KiB
LLVM
269 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
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; Test the zeroext/signext variants of each pattern to see if that makes a difference.
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; select Cond, 0, 1 --> zext (!Cond)
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define i32 @select_0_or_1(i1 %cond) {
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; CHECK-LABEL: select_0_or_1:
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; CHECK: # BB#0:
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; CHECK-NEXT: notb %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_0_or_1_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_1_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: notb %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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; select Cond, 1, 0 --> zext (Cond)
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define i32 @select_1_or_0(i1 %cond) {
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; CHECK-LABEL: select_1_or_0:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_1_or_0_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_1_or_0_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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; select Cond, 0, -1 --> sext (!Cond)
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define i32 @select_0_or_neg1(i1 %cond) {
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; CHECK-LABEL: select_0_or_neg1:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: leal -1(%rdi), %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_0_or_neg1_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_neg1_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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; select Cond, -1, 0 --> sext (Cond)
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define i32 @select_neg1_or_0(i1 %cond) {
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; CHECK-LABEL: select_neg1_or_0:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_neg1_or_0_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testb %dil, %dil
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_neg1_or_0_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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; select Cond, C+1, C --> add (zext Cond), C
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define i32 @select_Cplus1_C(i1 %cond) {
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; CHECK-LABEL: select_Cplus1_C:
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; CHECK: # BB#0:
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: andl $1, %edi
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; CHECK-NEXT: leal 41(%rdi), %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_Cplus1_C_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: addl $41, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_signext(i1 signext %cond) {
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; CHECK-LABEL: select_Cplus1_C_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: movzbl %dil, %eax
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; CHECK-NEXT: addl $41, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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; select Cond, C, C+1 --> add (sext Cond), C
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define i32 @select_C_Cplus1(i1 %cond) {
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; CHECK-LABEL: select_C_Cplus1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: cmpb $1, %dil
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: adcl $0, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_C_Cplus1_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: cmpb $1, %dil
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: adcl $0, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_C_Cplus1_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: andb $1, %dil
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; CHECK-NEXT: cmpb $1, %dil
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; CHECK-NEXT: movl $41, %eax
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; CHECK-NEXT: adcl $0, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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; In general, select of 2 constants could be:
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; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
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define i32 @select_C1_C2(i1 %cond) {
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; CHECK-LABEL: select_C1_C2:
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; CHECK: # BB#0:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
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; CHECK-NEXT: movl $42, %eax
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; CHECK-NEXT: cmovnel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_C1_C2_zeroext:
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; CHECK: # BB#0:
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; CHECK-NEXT: testb %dil, %dil
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; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
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; CHECK-NEXT: movl $42, %eax
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; CHECK-NEXT: cmovnel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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define i32 @select_C1_C2_signext(i1 signext %cond) {
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; CHECK-LABEL: select_C1_C2_signext:
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; CHECK: # BB#0:
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; CHECK-NEXT: testb $1, %dil
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; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5
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; CHECK-NEXT: movl $42, %eax
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; CHECK-NEXT: cmovnel %ecx, %eax
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; CHECK-NEXT: retq
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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; select (x == 2), 2, (x + 1) --> select (x == 2), x, (x + 1)
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define i64 @select_2_or_inc(i64 %x) {
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; CHECK-LABEL: select_2_or_inc:
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; CHECK: # BB#0:
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; CHECK-NEXT: leaq 1(%rdi), %rax
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; CHECK-NEXT: cmpq $2, %rdi
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; CHECK-NEXT: cmoveq %rdi, %rax
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; CHECK-NEXT: retq
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%cmp = icmp eq i64 %x, 2
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%add = add i64 %x, 1
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%retval.0 = select i1 %cmp, i64 2, i64 %add
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ret i64 %retval.0
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}
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