forked from OSchip/llvm-project
111 lines
3.9 KiB
LLVM
111 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86-64 -mcpu=corei7 -mattr=avx512vl | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
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define i64 @test_x86_sse2_cvtsd2si64(<2 x double> %a0) {
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; CHECK-LABEL: test_x86_sse2_cvtsd2si64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsd2si %xmm0, %rax
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone
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define <2 x double> @test_x86_sse2_cvtsi642sd(<2 x double> %a0, i64 %a1) {
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; CHECK-LABEL: test_x86_sse2_cvtsi642sd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
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ret <2 x double> %res
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}
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declare <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double>, i64) nounwind readnone
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define i64 @test_x86_sse2_cvttsd2si64(<2 x double> %a0) {
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; CHECK-LABEL: test_x86_sse2_cvttsd2si64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvttsd2si %xmm0, %rax
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
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define i64 @test_x86_sse_cvtss2si64(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_sse_cvtss2si64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtss2si %xmm0, %rax
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone
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define <4 x float> @test_x86_sse_cvtsi642ss(<4 x float> %a0, i64 %a1) {
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; CHECK-LABEL: test_x86_sse_cvtsi642ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0
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; CHECK-NEXT: retq
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%res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float>, i64) nounwind readnone
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define i64 @test_x86_sse_cvttss2si64(<4 x float> %a0) {
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; CHECK-LABEL: test_x86_sse_cvttss2si64:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vcvttss2si %xmm0, %rax
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; CHECK-NEXT: retq
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%res = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %a0) ; <i64> [#uses=1]
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ret i64 %res
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}
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declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone
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define <4 x double> @test_x86_avx_vzeroall(<4 x double> %a, <4 x double> %b) {
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; AVX-LABEL: test_x86_avx_vzeroall:
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; AVX: ## BB#0:
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; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vmovupd %ymm0, -{{[0-9]+}}(%rsp) ## 32-byte Spill
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; AVX-NEXT: vzeroall
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; AVX-NEXT: vmovups -{{[0-9]+}}(%rsp), %ymm0 ## 32-byte Reload
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; AVX-NEXT: retq
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;
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; AVX512VL-LABEL: test_x86_avx_vzeroall:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vaddpd %ymm1, %ymm0, %ymm16
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; AVX512VL-NEXT: vzeroall
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; AVX512VL-NEXT: vmovapd %ymm16, %ymm0
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; AVX512VL-NEXT: retq
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%c = fadd <4 x double> %a, %b
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call void @llvm.x86.avx.vzeroall()
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ret <4 x double> %c
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}
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declare void @llvm.x86.avx.vzeroall() nounwind
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define <4 x double> @test_x86_avx_vzeroupper(<4 x double> %a, <4 x double> %b) {
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; AVX-LABEL: test_x86_avx_vzeroupper:
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; AVX: ## BB#0:
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; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0
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; AVX-NEXT: vmovupd %ymm0, -{{[0-9]+}}(%rsp) ## 32-byte Spill
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: vmovups -{{[0-9]+}}(%rsp), %ymm0 ## 32-byte Reload
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; AVX-NEXT: retq
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;
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; AVX512VL-LABEL: test_x86_avx_vzeroupper:
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; AVX512VL: ## BB#0:
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; AVX512VL-NEXT: vaddpd %ymm1, %ymm0, %ymm16
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; AVX512VL-NEXT: vzeroupper
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; AVX512VL-NEXT: vmovapd %ymm16, %ymm0
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; AVX512VL-NEXT: retq
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%c = fadd <4 x double> %a, %b
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call void @llvm.x86.avx.vzeroupper()
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ret <4 x double> %c
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}
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declare void @llvm.x86.avx.vzeroupper() nounwind
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