llvm-project/llvm/test/CodeGen/Lanai
Francis Visoiu Mistrih 93ef145862 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
2017-11-30 12:12:19 +00:00
..
codemodel.ll [lanai] Simplify small section check in LowerGlobalAddress and treat ldata sections specially. 2016-12-15 16:56:16 +00:00
comparisons_i32.ll
comparisons_i64.ll
constant_multiply.ll
delay_filler.ll
i32.ll
lanai-misched-trivial-disjoint.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
lit.local.cfg
lshift64.ll [lanai] Custom lowering of SHL_PARTS 2016-12-02 22:01:28 +00:00
masking_setccs.ll [lanai] Add computeKnownBitsForTargetNode for Lanai. 2017-05-09 18:35:26 +00:00
mem_alu_combiner.ll
multiply.ll
peephole-compare.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
rshift64.ll
select.ll
set_and_hi.ll
shift.ll
stack-frame.ll
sub-cmp-peephole.ll
subword.ll