forked from OSchip/llvm-project
71dfb7ec5c
Make the FP register callee saved. This is tricky because now the FP needs to be spilled in the prolog relative to the incoming SP register, rather than the frame register used throughout the rest of the function. I don't like how this bypassess the standard mechanism for CSR spills just to get the correct insert point. I may look for a better solution, since all CSR VGPRs may also need to have all lanes activated. Another option might be to make getFrameIndexReference change the base register if the frame index is a CSR, and then try to figure out the right insertion point in emitProlog. If there is a free VGPR lane available for SGPR spilling, try to use it for the FP. If that would require intrtoducing a new VGPR spill, try to use a free call clobbered SGPR. Only fallback to introducing a new VGPR spill as a last resort. This also doesn't attempt to handle SGPR spilling with scalar stores. llvm-svn: 365372 |
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| .. | ||
| expected-target-index-name.mir | ||
| intrinsics.mir | ||
| invalid-target-index-operand.mir | ||
| lit.local.cfg | ||
| load-store-opt-dlc.mir | ||
| machine-function-info-no-ir.mir | ||
| machine-function-info-register-parse-error1.mir | ||
| machine-function-info-register-parse-error2.mir | ||
| machine-function-info.ll | ||
| mfi-frame-offset-reg-class.mir | ||
| mfi-parse-error-frame-offset-reg.mir | ||
| mfi-parse-error-scratch-rsrc-reg.mir | ||
| mfi-parse-error-scratch-wave-offset-reg.mir | ||
| mfi-parse-error-stack-ptr-offset-reg.mir | ||
| mfi-scratch-rsrc-reg-reg-class.mir | ||
| mfi-scratch-wave-offset-reg-class.mir | ||
| mfi-stack-ptr-offset-reg-class.mir | ||
| mir-canon-multi.mir | ||
| parse-order-reserved-regs.mir | ||
| stack-id.mir | ||
| syncscopes.mir | ||
| target-flags.mir | ||
| target-index-operands.mir | ||