llvm-project/llvm/test/CodeGen
Mikhail Maltsev 9c579540ff [ARM] BFloat MatMul Intrinsics&CodeGen
Summary:
This patch adds support for BFloat Matrix Multiplication Intrinsics
and Code Generation from __bf16 to AArch32. This includes IR intrinsics. Tests are
provided as needed.

This patch is part of a series implementing the Bfloat16 extension of
the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type and its properties are specified in the Arm
Architecture
Reference Manual:

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

The following people contributed to this patch:

 - Luke Geeson
 - Momchil Velikov
 - Mikhail Maltsev
 - Luke Cheeseman
 - Simon Tatham

Reviewers: stuij, t.p.northover, SjoerdMeijer, sdesmalen, fpetrogalli, LukeGeeson, simon_tatham, dmgreen, MarkMurrayARM

Reviewed By: MarkMurrayARM

Subscribers: MarkMurrayARM, danielkiss, kristof.beyls, hiraditya, cfe-commits, llvm-commits, chill, miyuki

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D81740
2020-06-23 12:06:37 +00:00
..
AArch64 [AArch64][SVE] ACLE: Add bfloat16 to struct load/stores. 2020-06-23 12:12:35 +01:00
AMDGPU [AMDGPU/MemOpsCluster] Compute `width` for `MIMG` instruction class. 2020-06-23 17:32:17 +05:30
ARC
ARM [ARM] BFloat MatMul Intrinsics&CodeGen 2020-06-23 12:06:37 +00:00
AVR [AVR] Rewrite the function calling convention. 2020-06-23 21:36:18 +12:00
BPF [BPF] fix a bug for BTF pointee type pruning 2020-06-17 15:13:46 -07:00
Generic [LLParser] Delete temp CallInst when error occurs 2020-06-16 11:41:25 +08:00
Hexagon Simplify MachineVerifier's block-successor verification. 2020-06-06 22:30:51 -04:00
Inputs
Lanai
MIR [MachineVerifier] Verify that a DBG_VALUE has a debug location 2020-05-28 13:53:40 -07:00
MSP430 Revert "[MSP430] Update register names" 2020-06-22 13:37:22 +03:00
Mips [DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) 2020-06-12 13:53:08 -04:00
NVPTX
PowerPC [PowerPC] fold addi's imm operand to its imm form consumer's displacement 2020-06-23 06:28:18 -04:00
RISCV [RISCV64] Emit correct lib call for fp(float/double) to ui/si 2020-06-18 19:34:16 +05:30
SPARC [SPARC] Lower fp16 ops to libcalls 2020-06-10 19:15:26 -07:00
SystemZ [SystemZ] Bugfix in storeLoadCanUseBlockBinary(). 2020-06-17 09:49:31 +02:00
Thumb
Thumb2 Revert "[CGP] Enable CodeGenPrepares phi type convertion." 2020-06-22 13:06:18 +02:00
VE [VE] Support relocation information in MC layer 2020-06-15 11:24:53 +02:00
WebAssembly [Target] As part of using inclusive language within the llvm project, 2020-06-20 00:06:39 -07:00
WinCFGuard
WinEH
X86 Revert "[X86][SSE] MatchVectorAllZeroTest - handle OR vector reductions" 2020-06-22 21:27:11 +02:00
XCore