forked from OSchip/llvm-project
68 lines
2.8 KiB
YAML
68 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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--- |
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define void @exp_compr_v2f16_s() {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
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ret void
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}
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define void @exp_compr_v2f16_v() {
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0)
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ret void
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}
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1)
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declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1)
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...
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---
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name: exp_compr_v2f16_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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; CHECK-LABEL: name: exp_compr_v2f16_s
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
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; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = COPY $sgpr0
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%3:_(s32) = COPY $sgpr1
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%6:_(s1) = G_CONSTANT i1 0
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%7:_(s1) = G_CONSTANT i1 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
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...
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---
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name: exp_compr_v2f16_v
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
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; CHECK-LABEL: name: exp_compr_v2f16_v
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
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; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1)
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%0:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(s32) = COPY $vgpr0
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%3:_(s32) = COPY $vgpr1
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%6:_(s1) = G_CONSTANT i1 0
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%7:_(s1) = G_CONSTANT i1 0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7
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...
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