forked from OSchip/llvm-project
39 lines
1.8 KiB
LLVM
39 lines
1.8 KiB
LLVM
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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;CHECK-LABEL: test1:
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;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
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;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
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define amdgpu_ps void @test1(<4 x float> inreg %reg0) {
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%r0 = extractelement <4 x float> %reg0, i32 0
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%r1 = extractelement <4 x float> %reg0, i32 1
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%r2 = call float @llvm.pow.f32( float %r0, float %r1)
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%vec = insertelement <4 x float> undef, float %r2, i32 0
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call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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ret void
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}
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;CHECK-LABEL: test2:
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;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
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;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
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;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
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;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
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;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
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;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
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;CHECK-NEXT: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}},
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;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}},
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
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;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}},
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define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
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%vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1)
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call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
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ret void
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}
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declare float @llvm.pow.f32(float ,float ) readonly
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declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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