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AArch64
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GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF
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2020-08-03 09:14:08 -04:00 |
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AMDGPU
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GlobalISel: Handle arbitrary FewerElementsVector for G_IMPLICIT_DEF
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2020-08-03 09:14:08 -04:00 |
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ARC
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…
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ARM
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[MachineCopyPropagation] BackwardPropagatableCopy: add check for hasOverlappingMultipleDef
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2020-07-29 16:21:01 +01:00 |
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AVR
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[AVR] Rewrite the function calling convention.
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2020-06-23 21:36:18 +12:00 |
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BPF
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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Generic
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[llc] (almost) remove `--print-machineinstrs`
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2020-07-20 10:43:28 -07:00 |
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Hexagon
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Align store conditional address
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2020-07-30 10:42:00 -05:00 |
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Inputs
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…
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Lanai
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…
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MIR
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AMDGPU: Serialize MFI spill fields
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2020-07-28 20:01:57 -04:00 |
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MSP430
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[MSP430] Declare comparison LibCalls as returning i16 instead of i32
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2020-06-30 11:04:22 +03:00 |
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Mips
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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NVPTX
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[NVPTX] Fix for NVPTX module asm regression
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2020-06-24 11:17:09 -07:00 |
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PowerPC
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[PPC] Adjust run line for hardware-loops-crash.ll
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2020-08-01 20:58:05 +01:00 |
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RISCV
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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SPARC
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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SystemZ
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[SystemZ] Ensure -mno-vx disables any use of vector features
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2020-07-23 15:34:59 +02:00 |
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Thumb
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…
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Thumb2
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[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz
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2020-08-03 13:20:32 +01:00 |
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VE
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[VE] Change calling convention to follow ABI
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2020-08-01 10:08:54 +09:00 |
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WebAssembly
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[WebAssembly] Fixed 64-bit indices in br_table
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2020-07-30 10:52:16 -07:00 |
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WinCFGuard
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…
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WinEH
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…
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X86
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[X86][SSE] Start shuffle combining from ANY_EXTEND_VECTOR_INREG on SSE targets
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2020-08-03 13:41:48 +01:00 |
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XCore
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…
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