llvm-project/llvm/test/CodeGen
Geoff Berry 2ddfc5e60f [DAGCombiner] Improve zextload optimization.
Summary:
Don't fold
  (zext (and (load x), cst)) -> (and (zextload x), (zext cst))
if
  (and (load x) cst)
will match as a zextload already and has additional users.

For example, the following IR:

  %load = load i32, i32* %ptr, align 8
  %load16 = and i32 %load, 65535
  %load64 = zext i32 %load16 to i64
  store i32 %load16, i32* %dst1, align 4
  store i64 %load64, i64* %dst2, align 8

used to produce the following aarch64 code:

	ldr		w8, [x0]
	and	w9, w8, #0xffff
	and	x8, x8, #0xffff
	str		w9, [x1]
	str		x8, [x2]

but with this change produces the following aarch64 code:

	ldrh		w8, [x0]
	str		w8, [x1]
	str		x8, [x2]

Reviewers: resistor, mcrosier

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14340

llvm-svn: 252789
2015-11-11 19:42:52 +00:00
..
AArch64 [DAGCombiner] Improve zextload optimization. 2015-11-11 19:42:52 +00:00
AMDGPU AMDGPU: Set isAllocatable = 0 on VS_32/VS_64 2015-11-11 00:01:32 +00:00
ARM [ARM] Combine BFIs together 2015-11-11 15:40:40 +00:00
BPF [bpf] Do not expand UNDEF SDNode during insn selection lowering 2015-10-08 18:52:40 +00:00
CPP Fix CPP Backend for GEP API changes for opaque pointer types 2015-09-08 18:42:29 +00:00
Generic Revert "[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll" 2015-10-29 22:34:59 +00:00
Hexagon [Hexagon] Fixing compound register printing and reenabling more tests. 2015-11-10 00:51:56 +00:00
Inputs DI: Reverse direction of subprogram -> function edge. 2015-11-05 22:03:56 +00:00
MIR MachineVerifier: Add missing linebreak 2015-11-09 23:59:29 +00:00
MSP430
Mips [mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes. 2015-11-06 12:07:20 +00:00
NVPTX [NVPTX] Let NVPTX backend detect integer min and max patterns. 2015-08-26 23:22:02 +00:00
PowerPC [PowerPC] Add an MI SSA peephole pass. 2015-11-10 21:38:26 +00:00
SPARC Drop assert that a call with struct return goes to a function with sret 2015-10-21 20:05:01 +00:00
SystemZ [SystemZ] Make the CCRegs regclass non-allocatable. 2015-10-29 16:13:55 +00:00
Thumb [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM. 2015-10-05 14:49:54 +00:00
Thumb2 [ARM] Handle t2ADDri in ARMAsmPrinter::EmitUnwindingInstruction. 2015-11-10 00:10:41 +00:00
WebAssembly [WebAssembly] Support non-legal argument and return types. 2015-11-11 01:33:02 +00:00
WinEH [WinEH] Re-committing r252249 (Clone funclets with multiple parents) with additional fixes for determinism problems 2015-11-09 19:59:02 +00:00
X86 [WinEH] Only generate UnwindHelp slot for MSVCXX 2015-11-11 19:21:09 +00:00
XCore DI: Reverse direction of subprogram -> function edge. 2015-11-05 22:03:56 +00:00