llvm-project/llvm/test/CodeGen
Nicolai Haehnle 1045928aab AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).

This is in preparation for the eventual removal of the old-style
intrinsics.

Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
  the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
  because %tmp1 was not used; remove the load, because it doesn't work
  (Because of the amdgpu_ps calling convention? In any case, it's
  orthogonal to what the test claims to be testing.)

Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf

Reviewers: arsenm, rampitec

Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D48018

llvm-svn: 335229
2018-06-21 13:37:19 +00:00
..
AArch64 [AArch64] Implement FLT_ROUNDS macro. 2018-06-20 12:09:01 +00:00
AMDGPU AMDGPU: Convert test cases to the dimension-aware intrinsics 2018-06-21 13:37:19 +00:00
ARC
ARM [DAGCombine] Fix alignment for offset loads/stores 2018-06-21 08:30:07 +00:00
AVR [AVR] Set trackLivenessAfterRegAlloc 2018-06-11 14:46:48 +00:00
BPF [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
Generic [DWARFv5] Tolerate files not all having an MD5 checksum. 2018-06-14 13:38:20 +00:00
Hexagon [Hexagon] Replace .ll test for expanding post-ra pesudos with .mir 2018-06-20 19:22:27 +00:00
Inputs
Lanai Remove SETCCE use from Lanai's backend 2018-06-03 12:56:24 +00:00
MIR [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property 2018-06-21 10:03:34 +00:00
MSP430 Emit a left-shift instead of a power-of-two multiply for jump-tables 2018-05-16 08:58:26 +00:00
Mips [mips] Add microMIPS specific addressing patterns. 2018-06-20 22:40:12 +00:00
NVPTX [DAG] fold FP binops with undef operands to NaN 2018-05-21 23:54:19 +00:00
Nios2
PowerPC [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property 2018-06-21 10:03:34 +00:00
RISCV [RISC-V] Fix a test case to not include label names as those aren't 2018-06-21 05:42:05 +00:00
SPARC [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SystemZ [BranchFolding] Fix live-in's when hoisting code 2018-06-07 07:20:33 +00:00
Thumb [ARM] Testcase for Thumb1 cmp with constants. 2018-06-19 00:12:13 +00:00
Thumb2 Generalize MergeBlockIntoPredecessor. Replace uses of MergeBasicBlockIntoOnlyPred. 2018-06-20 22:01:04 +00:00
WebAssembly [WebAssembly] Fix liveness tracking info after drop insertion 2018-06-19 20:30:42 +00:00
WinCFGuard
WinEH [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00
X86 [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property 2018-06-21 10:03:34 +00:00
XCore [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label. 2018-05-09 02:40:45 +00:00