Guillaume Chatelet 333f2ad8b8 [Alignment][NFC] Use Align for getMemcpy/Memmove/Memset ... Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, dschuff, jyknight, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73885		2020-02-03 17:13:19 +01:00
..
AsmParser	[RISCV] Implement jump pseudo-instruction	2020-01-31 22:28:26 +00:00
Disassembler	CMake: Make most target symbols hidden by default	2020-01-14 19:46:52 -08:00
MCTargetDesc	[RISCV] Implement jump pseudo-instruction	2020-01-31 22:28:26 +00:00
TargetInfo	CMake: Make most target symbols hidden by default	2020-01-14 19:46:52 -08:00
Utils	[RISCV] Support ABI checking with per function target-features	2020-01-22 08:12:28 -08:00
CMakeLists.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
LLVMBuild.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVAsmPrinter.cpp	CMake: Make most target symbols hidden by default	2020-01-14 19:46:52 -08:00
RISCVCallLowering.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallLowering.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallingConv.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Use addi rather than add x0	2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp	[RISCV] Allow shrink wrapping for RISC-V	2020-01-14 18:59:11 +00:00
RISCVFrameLowering.h	[RISCV] Handle variable sized objects with the stack need to be realigned	2019-11-16 12:39:53 +08:00
RISCVISelDAGToDAG.cpp	[SelectionDAG] Disallow indirect "i" constraint	2019-12-29 16:50:42 -08:00
RISCVISelLowering.cpp	[Alignment][NFC] Use Align for getMemcpy/Memmove/Memset	2020-02-03 17:13:19 +01:00
RISCVISelLowering.h	CodeGen: Use LLT instead of EVT in getRegisterByName	2020-01-09 17:37:52 -05:00
RISCVInstrFormats.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td	…
RISCVInstrInfo.cpp	[NFC] unsigned->Register in storeRegTo/loadRegFromStack	2020-02-03 14:22:16 +01:00
RISCVInstrInfo.h	[NFC] unsigned->Register in storeRegTo/loadRegFromStack	2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td	[RISCV] Implement jump pseudo-instruction	2020-01-31 22:28:26 +00:00
RISCVInstrInfoA.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoF.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstrInfoM.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Delete a ctor that is commented out. NFC	2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp	[RISCV] Handle variable sized objects with the stack need to be realigned	2019-11-16 12:39:53 +08:00
RISCVRegisterInfo.h	[TargetRegisterInfo] Default trackLivenessAfterRegAlloc() to true	2020-01-19 14:20:37 -08:00
RISCVRegisterInfo.td	[RISCV] Rename FPRs and use Register arithmetic	2019-09-27 15:49:10 +00:00
RISCVSchedRocket32.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVSchedRocket64.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVSchedule.td	[RISCV] Scheduler description for the Rocket core	2020-01-23 19:36:47 -06:00
RISCVSubtarget.cpp	Make llvm::StringRef to std::string conversions explicit.	2020-01-28 23:25:25 +01:00
RISCVSubtarget.h	[RISCV] Add support for -ffixed-xX flags	2019-10-22 21:25:01 +01:00
RISCVSystemOperands.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp	[RISCV] Check the target-abi module flag matches the option	2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h	[RISCV] Add subtargets initialized with target feature	2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp	Revert "Honor -fuse-init-array when os is not specified on x86"	2019-12-17 07:36:59 -08:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp	Rename TTI::getIntImmCost for instructions and intrinsics	2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h	Rename TTI::getIntImmCost for instructions and intrinsics	2019-12-11 18:00:20 -08:00