forked from OSchip/llvm-project
52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
{
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"arrays": [
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{
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"name": "MemRef_arg",
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"sizes": [
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"*"
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],
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"type": "i32"
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},
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{
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"name": "MemRef_arg2",
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"sizes": [
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"*"
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],
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"type": "i32"
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}
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],
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"context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }",
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"name": "%bb3---%bb19",
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"statements": [
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{
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"accesses": [
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{
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"kind": "read",
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"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }"
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},
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{
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"kind": "write",
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"relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg2[1 + i0] : arg1 <= 2305843009213693952 }"
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}
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],
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"domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }",
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"name": "Stmt_bb3__TO__bb10",
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"schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }"
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},
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{
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"accesses": [
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{
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"kind": "read",
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"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
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},
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{
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"kind": "write",
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"relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }"
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}
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],
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"domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }",
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"name": "Stmt_bb10",
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"schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }"
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}
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]
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} |