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llvm-project/llvm/lib/Target/RISCV/MCTargetDesc
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Alex Bradbury 893e5bc774 [RISCV] Support .option push and .option pop 
This adds support in the RISCVAsmParser the storing of Subtarget feature bits to a stack so that they can be pushed/popped to enable/disable multiple features at once.

Differential Revision: https://reviews.llvm.org/D46424
Patch by Lewis Revill.

llvm-svn: 347774
 		2018-11-28 16:39:14 +00:00
..
CMakeLists.txt Revert "[RISCV] implement li pseudo instruction" 2018-04-18 19:02:31 +00:00
LLVMBuild.txt
…
RISCVAsmBackend.cpp [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
RISCVAsmBackend.h [RISCV] Support .option relax and .option norelax 2018-11-12 14:25:07 +00:00
RISCVELFObjectWriter.cpp [RISCV] Support linker relax function call from auipc and jalr to jal 2018-05-24 06:21:23 +00:00
RISCVELFStreamer.cpp [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
RISCVELFStreamer.h [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
RISCVFixupKinds.h [RISCV] Support linker relax function call from auipc and jalr to jal 2018-05-24 06:21:23 +00:00
RISCVMCAsmInfo.cpp [RISCV] Add support for .half, .hword, .word, .dword directives 2018-05-17 05:58:08 +00:00
RISCVMCAsmInfo.h
…
RISCVMCCodeEmitter.cpp [RISCV] Support named operands for CSR instructions. 2018-10-04 21:50:54 +00:00
RISCVMCExpr.cpp [Target] Untangle disassemblers 2018-09-10 12:53:46 +00:00
RISCVMCExpr.h [RISCV] Support "call" pseudoinstruction in the MC layer 2018-04-25 14:18:55 +00:00
RISCVMCTargetDesc.cpp [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
RISCVMCTargetDesc.h MC: Separate creating a generic object writer from creating a target object writer. NFCI. 2018-05-21 19:20:29 +00:00
RISCVTargetStreamer.cpp [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00
RISCVTargetStreamer.h [RISCV] Support .option push and .option pop 2018-11-28 16:39:14 +00:00